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| features ? power supply control ? power supply control: power-on factor (2 external signals an d 2 internal signals) ? battery voltage detection ? reset detection ? thermal protection ? smpl (sudden momentary power loss) function power supply function ? step-down dc/dc converter 1 (one-shot pwm) ? ldo 9 (eco-mode for ldo1 and 3) ? over-current protection (a ll linear regulators) li-ion battery charger ? cc/cv charge ? internal p-mos, current sense resistor and schottky diode ? charge current control by chip temperature white led driver and charge pump ? white led driver for backlight: up to 25 ma/led x 4 ? white led driver charge pump: up to 100 ma rtc ? built-in coin charge regulator ? 32 khz crystal oscillator (wit h time adjustment function) ? 32 khz output audio codec ? voice codec: 16-bit linear codec ? audio dac: 16-bit linear stereo dac ? tone generator: supports 16 dtmf tones ? mono mic amplifier: differential amplifier ? stereo headphone amplifie r: 22 mw (32 ohm load) ? mono receiver amplifier: 60 mw (32 ohm btl load) ? mono speaker amplifier: 300 mw (8 ohm btl load) ? microphone bias supply : output voltage = 2.2v pll ? jack detect input 200 kohm pull-up cpu interface ? spi (max 10 mhz) others ? gpio 4ch2ch: common use with adc input ? 8-bit adc (battery monitor, charge current monitor, 2 channels of external input) package ? 96-pin csp package (body size: 9 x 9 x 1mm, pin pitch 0.8mm) process ? cmos process 6329a?pmaac?12-aug-07 power management and analog companions (pmaac) AT73C206 power management ic and audio codec
2 6329a?pmaac?12-aug-07 AT73C206 1. description the AT73C206 is the integrated analog device for voip and cellular phones. it integrates a power management ic, which includes ldo, dc/dc converter, li-ion battery charger, white led driver, charge pump, rtc and gpio, as well as audio codec in one chip. 2. pin configuration figure 2-1. pin configuration top view 12345678910 a b c d e f g h j k a xin xout keyled onsw pshold irqb p2 vddio vo1 vo3 b vin7 vsb gndkey vin6 onob adpinb p3 sen vdc1 vo4 c din3 din4 gndled smpl rstb p0 sdi sclk vin4 vo5 d din1 din2 cpout gndd out32k p1 sdo gnda refo vo6 ec1p c2pvin1ldo1sel smic bias vin5 vo7 vo8 f c1m c2m gndcp gsp smicp smicm micbias vo9 g vin3 vin2 fb j kdeti lrckio vss micp micm vddana vo10 h lx gnddc gndchg ckout dout din spom recop vddhp vssana j chgout imoni vcap ckin jkdeto bckio spop recom vsshp avref k chgadp vsspll acap vddpll vdd vbsp gndsp hpol hpor vcom 12345678910 to p view 3 6329a?pmaac?12-aug-07 AT73C206 3. typical application circuit ldo7 1.3v 20ma(pll) ldo3 2.5v 100ma(io) ldo4 1.8/2.8/3.0v 200ma(sim) ldo5 2.8/3.0/3.3v 100ma(vibrator) vref 2.0v ldo9 2.8v/100ma (analog audio) ldo8 1.8v/2.8v 150ma(display) 1uf 2.2uf 1uf 1uf 1uf 1uf 0.47uf vo3 vo4 vo5 vo7 vin5 vo8 vo9 refo 1uf vin4 1uf 1uf vo6 chgadp chgout imoni white led driver @25ma charge pump 4.8v/100ma 5bit dac 2.7k gndled 4.7uf ldo10 2.8v/100ma (digital audio) 1uf vo10 ldo1 0.9/1.0/1.3/1.5v 300ma(core) 2.2uf vo1 vdc1 bckio lrckio din vddana micm micp avref vcom din1 din2 din3 din4 c1p c1m c2p c2m 1.0uf 1.0uf cpout 2.2uf gndcp stepdown dc/dc converter 1.8v 650ma (io/mems) lx fb gnddc vin3 2.2uh 4.7uf 2.2uf vo2 vin2 1uf pll vddpll vcap acap vsspll audio dac logic vdd voice codec logic vss spop spom recop recom hpol hpor vbsp gndsp vddhp vsshp codec analog micbias vssana smic bias 2.2v/1ma gnda gpio p3 p2 p1/an1 p0/an0 spi sclk sdo sdi sen pwrcnt onob rstb pshold out32k gndd smpl onsw vin6 gndkey keypad led keyled oscreg xin xout rtc logic chg logic mic ac adaptor 5v resdet batdet tshut 0.1uf 0.1uf 1uf 1uf power sw li-ion battery speaker receiver headphone l headphone r keypad led irqb mic bias 2.2v/1ma smicm smicp smicbias mic 0.1uf sclko seno si ldo1sel 8bit adc dout vin7 coin charge vsb coin battery vin1 2.2uf gndchg jack detector jkdeto jkdeti 200k vdd adpinb li-ion linear charger 0.1uf vddio ldo6 1.3v 20ma(pll) ckin ckout gsp 1k 0.1uf 4 6329a?pmaac?12-aug-07 AT73C206 4. pin description table 4-1. pin description no. block pin name i/o if level description notes 1 rtc b2 vsb o power input of coin charge regulator output and rtc 2 b1 vin7 vcc vbat power supply for rtcreg 3 white led driver c2 din4 o backlight white led driver output 4 4 c1 din3 o backlight white led driver output 3 5 c3 gndled gnd gnd gnd for backlight white led driver 6 d2 din2 o backlight white led driver output 2 7 d1 din1 o backlight white led driver output 1 8 chg pump d3 cpout o charge pump output for white led driver 9 e2 c2p o voltage-boost capacitor connection pin for charge pump 10 e1 c1p o voltage-boost capacitor connection pin for charge pump 11 e3 vin1 vcc vbat power supply for charge pump 12 f1 c1m o voltage-boost capacitor connection pin for charge pump 13 f2 c2m o voltage-boost capacitor connection pin for charge pump 14 f3 gndcp gnd gnd gnd for charge pump 15 dc/dc g3 fb i output voltage feedback input of dc/dc converter 16 g2 vin2 vcc vbat power supply for dc/dc converter control block 17 g1 vin3 vcc vbat power supply for dc/dc converter driver 18 h1 lx o vbat dc/dc converter switch output 19 h2 gnddc gnd gnd gnd for dc/dc converter 20 charger h3 gndchg gnd gnd gnd for charger block filter connection pin for 21 j2 imoni o battery charge current monitor 22 j1 chgout o vbat li-ion battery charger output 23 k1 chgadp vcc acadp charger block power (ac adaptor connected) 24 pll k2 vsspll gnd gnd pll for gnd 25 j3 vcap o filter connection pin for voice pll 26 k3 acap o filter connection pin for audio pll 27 k4 vddpll vcc vo10 pll power 28 j4 ckin i clock input 29 h4 ckout o clock output 30 jackdet g4 jkdeti i jackdet input 31 j5 jkdeto o jackdet output 5 6329a?pmaac?12-aug-07 AT73C206 no block pin name i/o if level description notes 32 audio /voice k5 vdd vcc vo10 power supply for codec digital block 33 h5 dout o vdd voice codec output 34 g5 lrckio i/o vdd audio / voice interface l/r select input / output 35 j6 bckio i/o vdd audio / voice interface serial clock input / output 36 h6 din i vdd audio and voice interface serial data input 37 g6 vss gnd gnd gnd for codec digital block 38 k6 vbsp vcc vbat power supply for speaker amp 39 j7 spop o speaker amp output + 40 h7 spom o speaker amp output - 41 k7 gndsp gnd gnd gnd for speaker amp output 42 h8 recop o receiver amp output + 43 j8 recom o receiver amp output - 44 h9 vddhp vcc vo9 power supply for headphone amp output 45 k8 hpol o headphone output l 46 k9 hpor o headphone output r 47 j9 vsshp gnd gnd gnd for headphone amp 48 k10 vcom o reference voltage don't load this pin 49 j10 avref o reference voltage don't load this pin 50 g7 micp i mic input + 51 g8 micm i mic input - 52 h10 vssana gnd gnd gnd for analog codec 53 g9 vddana vcc vo9 power for analog codec 54 f7 smicp i smic input + 55 f8 smicm i smic input - 56 f9 micbias o mic bias output 57 e7 smicbias o smic bias output 58 ldo g10 vo10 o ldo10 output 59 f10 vo9 o ldo9 output 60 e8 vin5 vcc vbat power supply for ldo6, 7, 8, 9, 10 61 e10 vo8 o ldo8 output 62 e9 vo7 o ldo7 output 63 d10 vo6 o ldo6 output 64 d8 gnda gnd gnd gnd for analog circuit 65 d9 refo o capacitor connection pin for reference voltage source don't load this pin 6 6329a?pmaac?12-aug-07 AT73C206 no block pin name i/o if level description notes 66 ldo c10 vo5 o ldo5 output 67 c9 vin4 vcc vbat power supply for ldo3, 4, 5 and vref 68 b10 vo4 o ldo4 output 69 a10 vo3 o ldo3 output 70 a9 vo1 o ldo1 output 71 b9 vdc1 vcc vo2 power supply for ldo1(dc/dc output) 72 spi b8 sen i vddio spi enable input signal 73 c8 sclk i vddio spi clock input 74 d7 sdo o vddio spi data output 75 c7 sdi o vddio spi data input 76 a8 vddio vcc vo3 power supply for i/o 77 gpio b7 p3 i/o vddio general purpose i/o port 3 78 a7 p2 i/o vddio general purpose i/o port 2 79 d6 p1/an1 i/o vddio general purpose i/o port 1/adc input 1 80 c6 p0/an0 i/o vddio general purpose i/o port 0/adc input 0 81 power control b6 adpinb o vddio ac adaptor insertion detection output 82 a6 irqb o vddio interru pt request output 83 d5 out32k o vddio 32 khz oscillation output 84 c5 rstb o vddio reset output (low-active) 85 b5 onob o vddio inverted output signal of onsw. 86 a5 pshold i vddio signal input pin to maintain power-on. 87 d4 gndd gnd gnd gnd for digital circuit 88 c4 smpl i vbat smpl enable signal input pull-down 89 a4 onsw i vbat power-on switch enable signal input pull-down 90 b4 vin6 vcc vbat power supply for vbat detector and other circuits 91 e4 ldo1sel i vbat ldo1 initial value select input pin(1.5v or 1.3v) 92 f4 gsp i vbat initial state select input pin 93 keypad led a3 keyled o keypad led output (nch open-drain) 94 b3 gndkey gnd gnd gnd for keypad led driver 95 rtc a2 xout o 32.768khz crystal oscillator output 96 a1 xin i 32.768khz crystal oscillator input 7 6329a?pmaac?12-aug-07 AT73C206 5. functional blocks 5.1 power control & reset 5.1.1 power control & reset block diagram figure 5-1. power control & reset block diagram table 5-1. pin/signal description pin/signal name function level onsw power-on signal input pin vbat onob inverted output signal of onsw vddio smpl power-on hold time setting capacitor connection at smpl vddo pshold - signal input pin to maintain power-on - self-reset input pin vddio rstb cpu reset signal output pin vddio chgpon power-on signal from charger block (rapid charge signal) onsw smpl pshold l/s rtcpon l/s chgpon l/s (from chg) (from rtc) poweron (to ldo & dcdc) ps hold & self reset onob 1m vin6 1m 1m vin6 vddio vddio vin6 tshut 32khz (from rtc block) vddio rstb internal reset vbat batdet vin6 vin6 vin6 reset timer 32khz (from rtc) self reset pshold clkstp vo3 regoff pon batdet smpl resdet resdet resdetsel 8 6329a?pmaac?12-aug-07 AT73C206 note: pin & bit name (capital letter), signal nam e (lowercase), register name (r + capital letter) 5.1.2 power on/off operation the AT73C206 is asserted by onsw (external pin), rtcpon(rtc alarm interrupt), smpl (sud- den momentary power loss) or chgpon (power-on signal from charger block). figure 5-2. power on/off sequence 1. power on by onsw pin when the "h" signal is input into onsw pin at battery voltage over 3.1v, poweron signal goes "h" and dc/dc, ldo (gsp= ?l?:ldo1, 3, 6, 7, gsp= ?h?: ldo1,3,5,6,8) are turned on. onob goes ?l?. when the output voltage of ldo3 reaches 90% of its regulation voltage, the internal rtcpon rtc alarm interrupt signal clkstp 32 khz oscillator stop signal poweron dc/dc & ldo enable signal output table 5-1. pin/signal description pin/signal name function level t sres (20ms) batdet vbat (vin6) 3.1v onsw poweron dcdc (vdc1) resdet 90% rstb r dly (60ms) pshold smpl 1.5v smpl 0.7v pshold ldo's depend on external capasita vo3(ldo3):90% onob 9 6329a?pmaac?12-aug-07 AT73C206 reset timer starts and outputs ?l? through the rstb pin. cpu powers up and rstb pin becomes "h" after reset delay time 60ms (typ). after cpu finishes its system initialization, cpu will turn pshold to "h". the system can keep power on by holding this pshold at "h". for this operation, it needs to push pshold signal ?h? before onsw pin falls ?l?. if onsw falls ?l ? before pushing pshold ?h?, AT73C206 will power off. 2. power on by rtcpon signal when an interrupt generates in rtc block, rtcpon goes ?h? and AT73C206 powers on performing same power-on sequence as onsw. 3. power on by smpl pin when pshold goes "h", smpl becomes "h" through the internal diode. smpl keeps "h" by external capacitor even when the battery is momentarily disconnected. if it keeps "h" until battery is reconnected, AT73C206 powers on performing same power-on sequence as onsw. 4. power on by chgpon signal when ac adapter is inserted, AT73C206 enters to rapid charge mode and chgpon goes "h" and poweron signal goes ?h? irre spective of batdet output. pshold func- tions as same as when power-on by onsw. AT73C206 cannot perform power-off during rapid charge. figure 5-3. power on/off sequence by chgpon chgpon poweron dcdc (vdc1) resdet 90% rstb pshold smpl 1.5v smpl 0.7v pshold ldo's depend on external capasita rapid charge vo3(ldo3):90% chgonb = "1" r dly (60ms) t sres (20ms) 10 6329a?pmaac?12-aug-07 AT73C206 5.1.3 smpl operation when the battery loses contact momentarily due to impact or vibration on the handset by some event such as dropping the device, smpl remain s ?h? with capacitor and re-powers as the bat- tery is reconnected. the smpl ?h? maintain time depends on the capacitor size. to achieve this function, pull pshold ?h? before smpl falls down to 0.7v. figure 5-4. smpl operation timing 5.1.3.1 relation of smpl-high-maintain-time vs. capacitor when momentary power loss figure 5-5. smpl-high-maintain-time when momentary power loss (vin6 = 3.6v) 5.1.4 voltage detector the AT73C206 has two voltage detectors in power control block, batdet and resdet. bat- det detects low battery voltage and resdet detects the ldo3 output voltage and generates battery voltage smpl pshold 0.7v power on factor dcdc ldo's c[uf] time[ms] 0.10 157 0.22 345 0.47 738 1.00 1570 0 200 400 600 800 1000 1200 1400 1600 1800 00. 20. 40. 60. 811. 2 capaci to r uf ti me ms 11 6329a?pmaac?12-aug-07 AT73C206 the reset signal through rstb pin. resdet needs to change by ldo3 output voltage set. when raise ldo3 output setting voltage, set ldo3 output voltage by ldo3sel bit first and then change resdet voltage by resdetsel bit with 200us of delay time. adversely, when lower ldo3 output setting voltage, resdetsel bit should be set prior to ldo3sel bit. figure 5-6. vo3 and resdet control timing 5.1.5 batdet electrical characteristic operating conditions (unless otherwise specified) t a = 25 c. 5.1.6 resdet electrical characteristic operating conditions (unless otherwise specified) vin = 3.6v, t a = 25 c. 5.1.7 rstb electrical characteristic operating conditions (unless otherwise specified) vin = 3.6v, t a = 25 c. 200us (min) (85%) (85%) (85%) vo3 rv det 0us(min) table 5-2. batdet electrical characteristics symbol parameter condition min typ max units bv rel batdet cancellation voltage battery voltage rising -3 % 3.1 +3 % v bv det batdet detection voltage battery voltage falling 2.9 v table 5-3. resdet electrical characteristics symbol parameter condition min typ max units rv rel resdet cancellation voltage vo3 voltage rising -3 90 +3 % rv det resdet detection voltage vo3 voltage falling 85 % table 5-4. rstb electrical characteristics symbol parameter condition min typ max units r dly reset delay timer delay time from vo390% to rstb = ?h? 60 ms 12 6329a?pmaac?12-aug-07 AT73C206 5.1.8 thermal shutdown circuit the thermal shutdown circuit consists of thermal detection circuit and comparator. 5.1.8.1 thermal shutdown block diagram figure 5-7. thermal shutdown block diagram 5.1.8.2 thermal shutdown explanation of operation thermal shutdown circuit detects overheat state by comparing the output voltages of thermal detection circuit and refo. if the overheat state is detected, AT73C206 will turn off to protect itself from overheating. it is impossible to power on AT73C206 at overheat state. 5.1.8.3 target thermal shutdown electrical characteristics operating conditions (unless otherwise specified) vin = 3.6v 5.1.9 self-reset by pshold when pshold pin is held at ?l? more than 20 ms, AT73C206 powers off as described in section 5.1.2 ?power on/off operation? on page 8 . however, if pshold pin is pushed up ?h? within 20 ms, the AT73C206 will conduct self-reset by rstb= ?l? for 60 ms. when self-reset, the dc/dc and ldos are all rese t to initial state since all the register is initialized. after self-reset, AT73C206 maintains power-on by pshold="h" as same as when normal power-on. pon regoff thermal detection circuit refo vin6 table 5-5. thermal shutdown electrical characteristics symbol parameter condition min typ max units t det detected temperature 140 t ret return temperature 110 i ss1 supply current ta = 25 c 5 15 ua i ss2 standby current ta = 25 c1ua 13 6329a?pmaac?12-aug-07 AT73C206 figure 5-8. self-reset 5.1.10 oscillator stop if the 32 khz clock oscillator stops, clkstp si gnal goes "h" and self-r eset function becomes invalid. in this case, pshold= ?l? will power off the AT73C206. also, when the 32 khz clock oscillator stop s, AT73C206 generate s an interrupt. (see ?power-on reset and oscillator stop detection function? on page 42 .) 5.2 regulators the AT73C206 has 9 low drop output regulators. the output voltage of ldo1, 3, 4, 5 and 8 are programmable. ldo1 must be power supplied by dc/dc output (1.8v) and the other ldos are power supplied by battery. the initial output voltage of ldo1 is selectable by ldo1sel pin or gsp pin. after power-on, the ldo1 output voltage is programmable via spi. after power-on, the output voltages for ldo3, 4, 5 and 8 are programmable via spi. power on/off of ldo4 to 10 regulators and switchover between eco-mode and normal-mode of ldo1 and 3 are controllable via spi. for optimized phase compensation, the bypass capacitor must be ceramic type. vref regulator provides reference voltage to ldo1, 3, 5, 6, 7, 10, resdet and tshut. rstb pshold initial on ldos and dcdc initial off ldos (60ms) 20ms or less power-on by programm is possible 20ms or more 100ms push pshold pin "h" within 20 ms. (20ms) poweron t dly t sres t pshold table 5-6. self-reset electrical characteristics symbol parameter condition min typ max units t sres self-reset time 20 ms t pshold pshold time 100 ms 14 6329a?pmaac?12-aug-07 AT73C206 5.2.1 ldo regulator block diagram figure 5-9. ldo regulator block diagram ldo1 (core) dcdc (io/mems) ldo3 (io) ldo4 (sim) ldo5 (vibrator) ldo7 (pll) ldo8 (display) ldo9 (audio-a) ldo10 (audio-d) 2.2uf 4.7uf 1uf 2.2uf 1uf 1uf 1uf 1uf 1uf vo1 vo2 vo3 vo4 vo5 vo6 1uf vo7 vo8 vo9 vo10 vref 0.47uf refo vin5 vin4 vdc1 vin2 vin3 power control ldoen ldo4on ldo5on ldo8on ldo9on ldo10on poweron ldo6on ldo7on ldo1cnt ldo1dac opmode1 ldo3cnt opmode3 ldo4cnt ldo4dac ldo5cnt ldo5dac ldo8cnt ldo8sel ldo1sel ldo3sel ldo6 (pll) gsp 15 6329a?pmaac?12-aug-07 AT73C206 5.2.2 linear regulators table table 5-7. linear regulators table gsp ldo1 (core) ldo3 (io) ldo4 (sim) ldo5 (vibrator) ldo6 (pll) ldo7 (pll) ldo8 (display) ldo9 (audio analog) ldo10 (audio digital) initial value l 1.3v/1.5v (ldo1sel) 2.5v 1.8v 3.0v 1.3v 1.3v 1.8v 2.8v 2.8v h 1.3v/1.5v (ldo1sel) 2.8v 1.8v 2.8 v 2.8v output current max 300ma 100ma 200ma 100ma 20ma 20ma 150ma 100ma 100ma programmable output voltage 0.9v 1.0v 1.3v 1.5v 2.5v 2.8v 3.0v 1.8v 2.8v 3.0v 3.1v 2.7v 2.8v 3.0v 3.3v fixed fixed 1.8v 2.8v fixed fixed initial state l on on off off on on off off off h on on off on on off on off off eco-mode yes yes no no no no no no no on/off control spi (ldo4on) spi (ldo5on) spi (ldo6on) spi (ldo7on) spi (ldo8on) spi (ldo9on) spi (ldo10on) bypass capacitor (c out ) 2.2uf 1.0uf 2.2uf 1.0uf 1.0uf 1.0uf 1.0uf 1.0uf 1.0uf table 5-8. recommended capacitor capacitor manufacturer model no 2.2 uf taiyo yuden ? jmk107bj225ka 1.0 uf taiyo yuden ? jmk105bj105kvb 16 6329a?pmaac?12-aug-07 AT73C206 5.2.3 eco-mode of ldo1 and 3 during eco-mode, ldo1 and 3 are operating on the low bias current for reducing the power consumption. when cpu are in sleep state or low power state, eco-mode makes it possible to keep outputting voltage to peripheral ics at low power consumption current. the maximum output current in eco-mode is half as much as in normal-mode. ldo1 and 3 can be eco-mode by setting the corresponding bits to the operation mode control register opmode1and opmode3. 5.2.3.1 timing chart of switchover between eco-mode and normal-mode figure 5-10. transition from normal to eco, eco to normal note: when operation mode is changed, AT73C206 has 1ms of transition time. mode transition is not recommendable during this mode transition time (1 ms). the maximum output current during tran- sition is same as eco-mode. 1ms 1ms transition time transition time normal-mode eco-mode normal-mode opmode bit write ("1") opmode bit write ("0") 17 6329a?pmaac?12-aug-07 AT73C206 5.2.4 ldo1 electrical characteristic 5.2.4.1 normal mode operating normal conditions (unless otherwise specified): vddin1 = dcdc out = 1.8v, c out = 2.2uf, t a = 25 c. table 5-9. ldo1 normal mode elec trical characteristics symbol parameter condition min typ max units vout1 output voltage 1.8v(-3%) vddin1 1.8v(+3%) 50ua < iout1 < ioutmax -3% 1.3/1.5 +3% v iout1 output current ----- 300 ma isht1 short current vo1=0v 200 ma ? vout1 ? vin line regulation 1.8v(-3%) vddin1 1.8v(+3%) iout1 = ioutmax/2 10 mv ? vout1 ? iout1 load regulation 50ua < iout1 < ioutmax 30 mv ? vout1 ? t a output voltage temperature coefficient -40 c t a 85 c+ 100 ppm rr1 ripple rejection f=1khz, iout1= ioutmax/2 60 db en1 output noise (rms) bw=100hz-100khz, iout1= ioutmax/2 70 uvrms iss1 supply current (iout1=0ma) 80 ua ioff1 standby current iout1=0ma 1 ua v tr 1 rising time iout1= 0ma vo1 > vout1 x 90% 200 us v tf1 falling time iout1=0ma vo1 < 0.5v 500 us pout1 programmable output voltage iout1= ioutmax/2 0.9v 1.0v 1.3v 1.5v v 18 6329a?pmaac?12-aug-07 AT73C206 5.2.4.2 eco mode table 5-10. ldo1 eco mode electrical characteristics symbol parameter condition min typ max units vout1 output voltage 1.8v(-3%) vddin1 1.8v(+3%) iout1= ioutmax/2 -3% 1.3/1.5 +3% v iout1 output current ----- 150 ma isht1 short current vo1=0v 200 ma iss1 supply current iout1= 0ma 3 ua pout1 programmable output voltage iout1= ioutmax/2 -4% 0.9v 1.0v +4% v -3% 1.3v 1.5v +3% 19 6329a?pmaac?12-aug-07 AT73C206 5.2.5 ldo3 electrical characteristic 5.2.5.1 normal mode operating normal conditions (unless otherwise specified): vin = 3.6v, c out = 1uf, t a = 25 c 5.2.5.2 eco mode table 5-11. ldo3 normal mode elec trical characteristics symbol parameter condition min typ max units vout3 output voltage 3.1v vin 4.2v 50ua < iout3 < ioutmax -3% 2.5 +3% v iout3 output current ----- 100 ma isht3 short current vo3=0v 60 ma ? vout3 ? vin line regulation 3.1v vin 4.2v iout3=ioutmax/2 10 mv ? vout3 ? iout3 load regulation 50ua < iout3 < ioutmax 20 mv ? vout3 ? t a output voltage temperature coefficient -40 c t a 85 c+ 100 ppm rr3 ripple rejection f=1khz, iout3= ioutmax/2 60 db en3 output noise (rms) bw=100hz-100khz, iout3= ioutmax/2 100 uvrms iss3 supply current (iout3=0ma) 50 ua ioff3 standby current iout3=0ma 1 ua v tr 3 rising time iout3= 0ma vo3 > vout3 x 90% 200 us v tf3 falling time iout3=0ma vo3 < 0.5v 500 us pout3 programmable output voltage iout3= ioutmax/2 -3% 2.5v 2.8v 3.0v +3% v table 5-12. ldo3 eco mode electrical characteristics symbol parameter condition min typ max units vout3 output voltage 3.1v vin 4.2v iout3= ioutmax/2 -3% 2.5 +3% v iout3 output current ----- 50 ma isht3 short current vo3=0v 60 ma iss3 supply current iout3= 0ma 3 ua pout3 programmable output voltage iout3= ioutmax/2 -3% 2.5v 2.8v 3.0v +3% v 20 6329a?pmaac?12-aug-07 AT73C206 5.2.6 ldo4 electrical characteristic operating conditions (unless otherwise specified) vin = 3.6v, c out = 2.2uf, t a = 25 c. table 5-13. ldo4 electrical characteristics symbol parameter condition min typ max units vout4 output voltage 3.1v vin 4.2v 50ua < iout4 < ioutmax -3% 1.8 +3% v iout4 output current ----- 200 ma isht4 short current vo4=0v 100 ma ? vout4 ? vin line regulation 3.1v vin 4.2v iout4=ioutmax/2 10 mv ? vout4 ? iout4 load regulation 50ua < iout4 < ioutmax 30 mv ? vout4 ? t a output voltage temperature coefficient -40 c t a 85 c+ 100 ppm rr4 ripple rejection f=1khz, iout4 = ioutmax/2 60 db en4 output noise (rms) bw=100hz-100khz, iout4= ioutmax/2 50 uvrms iss4 supply current (iout4=0ma) 80 ua ioff4 standby current iout4=0ma 1 ua v tr 4 rising time iout4= 0ma vo4 > vout4 x 90% 200 us v tf4 falling time iout4=0ma vo4 < 0.5v 500 us pout4 programmable output voltage iout4 = ioutmax/2 1.8v 2.8v 3.0v 3.1v v 21 6329a?pmaac?12-aug-07 AT73C206 5.2.7 ldo5 electrical characteristic operating conditions (unless otherwise specified): vin = 3.6v, c out = 1 uf, t a = 25 c. table 5-14. ldo5 electrical characteristics symbol parameter condition min typ max units vout5 output voltage 3.1v vin 4.2v 50ua < iout5 < ioutmax -3% 3.0 +3% v iout5 output current ----- 100 ma isht5 short current vo5=0v 60 ma ? vout5 ? vin line regulation 3.1v vin 4.2v iout5=ioutmax/2 10 mv ? vout5 ? iout5 load regulation 50ua < iout5 < ioutmax 20 mv ? vout5 ? t a output voltage temperature coefficient -40 c t a 85 c+ 100 ppm/ iss5 supply current iout5 = 0ma 50 ua ioff5 standby current iout5 = 0ma 1 ua v tr 5 rising time iout5= 0ma vo5 > vout5 x 90% 200 us v tf5 falling time iout5=0ma vo5 < 0.5v 500 us pout5 programmable output voltage iout5 = ioutmax/2 2.8v 3.0v 3.3v v 22 6329a?pmaac?12-aug-07 AT73C206 5.2.8 ldo6 electrical characteristic operating conditions (unless otherwise specified): vin = 3.6v, c out = 1uf, t a = 25 c. table 5-15. ldo6 electrical characteristics symbol parameter condition min typ max units vout6 output voltage 3.1v vin 4.2v 50ua < iout6 < ioutmax -3% 1.3 +3% v iout6 output current ----- 20 ma ? vout6 ? vin line regulation 3.1v vin 4.2v iout6 = ioutmax/2 10 mv ? vout6 ? iout6 load regulation 50ua < iout6 < ioutmax 10 mv ? vout6 ? t a output voltage temperature coefficient -40 c t a 85 c+ 100 ppm/ rr6 ripple rejection f=1khz, iout6= ioutmax/2 60 db iss6 supply current (iout6=0ma) 50 ua ioff6 standby current iout6=0ma 1 ua v tr 6 rising time iout6=0ma vo6 > vout6 x 90% 200 us v tf6 falling time iout6=0ma vo6 < 0.5v 500 us 23 6329a?pmaac?12-aug-07 AT73C206 5.2.9 ldo7 electrical characteristic operating conditions (unless otherwise specified) vin = 3.6v, c out = 1uf, t a = 25 c. table 5-16. ldo7 electrical characteristics symbol parameter condition min typ max units vout7 output voltage 3.1v vin 4.2v 50ua < iout7 < ioutmax -3% 1.3 +3% v iout7 output current ----- 20 ma ? vout7 ? vin line regulation 3.1v vin 4.2v iout7 = ioutmax/2 10 mv ? vout7 ? iout7 load regulation 50ua < iout7 < ioutmax 10 mv ? vout7 ? t a output voltage temperature coefficient -40 c t a 85 c+ 100 ppm/ rr7 ripple rejection f=1khz, iout7= ioutmax/2 60 db iss7 supply current (iout7=0ma) 50 ua ioff7 standby current iout7=0ma 1 ua v tr 7 rising time iout7=0ma vo7 > vout7 x 90% 200 us v tf7 falling time iout7 = 0ma vo7 < 0.5v 500 us 24 6329a?pmaac?12-aug-07 AT73C206 5.2.10 ldo8 electrical characteristic operating conditions (unless otherwise specified) vin = 3.6v, c out = 1uf, t a = 25 c. table 5-17. ldo8 electrical characteristics symbol parameter condition min typ max units vout8 output voltage 3.1v vin 4.2v 50ua < iout8 < ioutmax -3% 1.8 +3% v iout8 output current ----- 150 ma isht8 short current vo8=0v 100 ma ? vout8 ? vin line regulation 3.1v vin 4.2v iout8=ioutmax/2 10 mv ? vout8 ? iout8 load regulation 50ua < iout8 < ioutmax 30 mv ? vout8 ? t a output voltage temperature coefficient -40 c t a 85 c+ 100 ppm/ rr8 ripple rejection f=1khz, iout8= 30ma 70 db en8 output noise (rms) bw=100hz-100khz, iout8=30 ma 50 uvrms iss8 supply current iout8 = 0ma 100 ua ioff8 standby current iout8 = 0ma 1 ua v tr 8 rising time iout8= 0ma vo8 > vout8 x 90% 200 us v tf8 falling time iout8=0ma vo8 < 0.5v 500 us pout8 programmable output voltage iout8 = ioutmax/2 1.8 2.8 v 25 6329a?pmaac?12-aug-07 AT73C206 5.2.11 ldo9 electrical characteristic operating conditions (unless otherwise specified) vin = 3.6v, c out = 1uf, t a = 25 c. table 5-18. ldo9 electrical characteristics symbol parameter condition min typ max units vout9 output voltage 3.1v vin 4.2v 50ua < iout9 < ioutmax -3% 2.8 +3% v iout9 output current ----- 100 ma isht9 short current vo9=0v 60 ma ? vout9 ? vin line regulation 3.1v vin 4.2v iout9=ioutmax/2 10 mv ? vout9 ? iout9 load regulation 50ua < iout9 < ioutmax 20 mv ? vout9 ? t a output voltage temperature coefficient -40 c t a 85 c+ 100 ppm/ rr9 ripple rejection f=1khz, iout9=ioutmax/2 70 db en9 output noise (rms) bw=100hz-100khz, iout9=ioutmax/2 50 uvrms iss9 supply current iout9 = 0ma 100 ua ioff9 standby current iout9 = 0ma 1 ua v tr 9 rising time iout9= 0ma vo9 > vout9 x 90% 200 us v tf9 falling time iout9=0ma vo9 < 0.5v 500 us 26 6329a?pmaac?12-aug-07 AT73C206 5.2.12 ldo10 electrical characteristic operating conditions (unless otherwise specified) vin = 3.6v, c out = 1uf, t a = 25 c. table 5-19. ldo10 electrical characteristics symbol parameter condition min typ max units vout10 output voltage 3.1v vin 4.2v 50ua < iout10 < ioutmax -3% 2.8 +3% v iout10 output current ----- 100 ma isht10 short current vo10=0v 60 ma ? vout10 ? vin line regulation 3.1v vin 4.2v iout10=ioutmax/2 10 mv ? vout10 ? iout10 load regulation 50ua < iout10 < ioutmax 20 mv ? vout10 ? t a output voltage temperature coefficient -40 c t a 85 c+ 100 ppm/ rr10 ripple rejection f=1khz, iout10=ioutmax/2 60 db en10 output noise (rms) bw=100hz-100khz, iout10=ioutmax/2 110 uvrms iss10 supply current iout10 = 0ma 50 ua ioff10 standby current iout10 = 0ma 1 ua v tr 1 0 rising time iout10= 0ma vo10 > vout10 x 90% 200 us v tf10 falling time iout10=0ma vo10 < 0.5v 500 us 27 6329a?pmaac?12-aug-07 AT73C206 5.3 step-down dc/dc converter AT73C206 has a one-shot pwm dc/dc converter. it employs external inductor and capacitor for smoothing output voltage and also external r 1 , r 2 and cf for both voltage setting and phase compensation. the control circuit is power supplied by vin2 and the switch transistor is power supplied by vin3. AT73C206 features soft-start to reduce inrush current at power-on and current limit circuit for over-current protection. 5.3.1 step-down dc/dc converter block diagram figure 5-11. step-down dc/dc converter block diagram 5.3.2 step-down dc/dc converter operation during standby mode, lx pin is high impedance. when dc/dc becomes active, the internal soft-start circuit is enabled and output voltage starts boosting. AT73C206 compares internal ref- erence voltage (typ.0.6v) and fb voltage. if fb voltage is below the reference voltage, it turns on high-side switch by enabling one-shot circuit. the high-side switch remains on for minimum-on-time or until fb voltage rises over the refer- ence voltage or inductor current exceeds limit current. once the high-side switch is disabled, it remains off until fb voltage falls below the refe rence voltage or inductor current falls below the limit current. during high-side switch is off, low-side switch remains on until inductor current approaches 0. the dc/dc converter regulates the output voltage by repeating the above operation. therefore, oscillator fre quency varies by input vo ltage, output vo ltage, output cu rrent and exter- nal circuit (r1, l, cf). in addition, the feedback loop from lx pin through r1 and from vo2 through cf eliminate phase lag by output capacitor providing the stable loop and fast transient response. gnddc lx cf switching control circuit vin3 l gnd fb current limit vo2 c out soft-start dcdc vref one-shot circuit vin2 gnd r 2 r 1 gnd + poweron 28 6329a?pmaac?12-aug-07 AT73C206 however, the output voltage is reduced by output current on dcr of inductor. (theoretically, output voltage falls [iout(a) x dcr(ohm)]) 5.3.3 output voltage setting calculation formula use the external components below for vout2=1.8v. l=2.2 uh, r 1 =200 k ? , r 2 =100 k ? , vout2=1.8v, cf=110 pf, cout=4.7 uf 5.3.4 step-down dc/dc converter electrical characteristic operating conditions (unless otherwise specified): vin=3.6v, t a = 25 c, l=2.2uh, cout=4.7uf note: load regulation, which is determined by dc resistance (dcr) on inductor, is given by: load regulation(typ) = dcr( ? ) x ioutda (a) for example, if dcr is 100 m ? ; dc/dc step down lx vin fb gnddc gnd gnd vo2 2.2uh 4.7uf cf =100k r 1 vout2 = output voltage r 1 = upper part resistance (r 1 +r 2 ) 0.6 r 2 vout2 = c f P l 10 (0.6v) gnd r 2 the output voltage can be calculated by formular below. the phase margin capacitor is determined by formular below. r 1 table 5-20. step-down dc/dc converter electrical characteristics symbol parameter condition min typ max units v batt input voltage 3.1 4.2 v vout2 output voltage range 0.9 1.8 2.5 v ioutd output current v in =3.1 to 4.2v 650 ma issd consumption current v in =3.1 to 4.2v ioutd=0ma, no switching 80 ua ioffd standby current v in =4.2v off state 1ua ilimd limit detection current 800 ma vfb fb voltage -1.5% 0.6 +1.5% v ? vfb ? vin fb line regulation v in =3.1 to 4.2v ioutd= ioutmax/2 5mv h efficiency r1=200 k ? , r2=100 k ? , cf=110 pf, ioutd=200ma 90 t r rising time soft-start 120 us ? vfb ? t fb voltage temperature coefficient -30 ta +85 100 ppm/ tonmin minimum-on-time 100 ns 29 6329a?pmaac?12-aug-07 AT73C206 0.1 ? x 0.65a = 65 mv (typ.) 5.4 white led driver and charge pump 5.4.1 charge pump the AT73C206 integrates boost charge pump for white led driver. for maximized power effi- ciency, the charge pump operates in 1x mode, 1.5x mode and 2x mode. it includes over-voltage lockout circuit to control the output voltage below the over-voltage detection voltage and soft- start circuit to prevent excessive inrush current at power-on. the charge pump is on except when ledcnt register is set to ?0?. 5.4.2 white led driver the AT73C206 white led driver drives up to 4 white leds with regulated constant current. it integrates 5-bit dac and performs the brightness control in 32-step by register set. 5.4.3 block diagram figure 5-12. white led driver and charge pump block diagram 5.4.4 charge pump operation 5.4.4.1 initial when AT73C206 powers on, the charge pump initially starts in 1x mode and vout outputs vin voltage. at this moment, the built-in soft-start circuit prevents excessive inrush current. see (1) in figure 5-13 on page 31 . 5.4.4.2 1x mode the charge pump switches to 1.5x mode if any din pin meets the following condition: din<0.25v vin1 gnd charge pump feed back c2m c1m cpout gndcp din1 din2 din3 din4 white led driver 5-bit dac current control on c2p c1p gnd 2.2uf gndled current setting signal on rledcnt 2.2uf 1.0uf 1.0uf 30 6329a?pmaac?12-aug-07 AT73C206 see (2) in figure 5-13 on page 31 . 5.4.4.3 1.5x mode the charge pump switches to 2x mode if any din pin meets the following condition: din<0.25v see (3) in figure 5-13 on page 31 . every second, charge pump switches to 1x che ck mode only for 100us. then it switches to: 1x mode if any din pin meets the following condition: din>0.4v see (5) in figure 5-13 on page 31 . 1.5x mode if any din pin m eets the following condition: din<0.4v see (6) in figure 5-13 on page 31 . 5.4.4.4 2x mode every second, charge pump switches to 1.5x check mode for 100us. then it switches to: 1.5x mode if any din pin m eets the following condition: din>0.4v see (8) in figure 5-13 on page 31 . 2x mode if any din pin meets the following condition: din<0.4v see (9) in figure 5-13 on page 31 . 31 6329a?pmaac?12-aug-07 AT73C206 5.4.4.5 1x/1.5x/2x mode transition figure 5-13. mode transition diagram 5.4.5 protection circuit when any din pin is floating or grounded duri ng operation, charge pump pin switches over to 2x mode following mode transition sequence. at t hat time, over-voltage lockout circuit regulates output voltage below the protection voltage by on/off boost operation periodically. besides, when cpout is smaller than 1.2v, short-circuit protection stops boost-operation and regulates output current. in addition, the protection operation halts when charge pump stops. 5.4.6 unused din pin in case there is any unused dinx pin, connect it to gnd. then, the AT73C206 recognizes the unused pin at power-on and then excludes it from mode transition condition. 5.4.7 target charge pump and white led driver electrical characteristics unless noted, vin=3.6v, ta=25 c, c1=c2=1uf, cout=2.2uf initial cpout = 0v soft start 1x mode 1.5x mode 2x mode 1x check mode(100us) 1.5x check mode(100us) cpout = 0v -> vin (1) (2) din < 0.25v (3) din < 0.25v (4) every second (5) din > 0.4v (6) din < 0.4v (7) every second (8) din > 0.4v (9) din < 0.4v 32 6329a?pmaac?12-aug-07 AT73C206 table 5-21. charge pump and white led driver electrical characteristics symbol parameter conditions min typ max units charge pump vin operation voltage range vin1 voltage 3.1 4.5 v v ovlv over-voltage lockout voltage repeat on/off 4.8 v iout output current vin1>3.1v, cpout=4.2v 100 ma f cp switching frequency 1.25 mhz t s soft-start time 0.3 ms iss supply current 1x mode, no load, (det, reference on) 500 ua 1.5x mode or 2x mode 5 ma ioff standby supply current vin1 current 1 ua isht short current cpout=0v 50 ma white led driver iled sink current range din1-4 0 25 ma iacc led current accuracy idin =25ma=1fh, dinx=0.25v -5 5 % imat led current matching -3 3 % vtth 1x to 1.5x, 1.5x to 2x transition threshold voltage if any pin among din1-4 falls under, 250 mv vthys 1x to 1.5x, 1.5x to 2x transition hysteresis voltage 150 mv ttr 1x to 1.5x, 1.5x to 2x transition time 100 us ilsd din1-4 leakage current when shut-down 0.01 ua 33 6329a?pmaac?12-aug-07 AT73C206 5.5 li-ion battery charger 5.5.1 description the li-ion battery charger contains a charge regulator, charge control circuit, charge current monitor, ac adapter detector, ac adaptor over-voltage detector and chip temperature detector. it has 2 charge modes, trickle charge and rapid charge, the charge current of which is con- trolled by registers. when AT73C206 detects that chip temperature approaches the die temperature by chip temper- ature detector, which is user selectable by register, it reduces charge current to 20% of charge current. when AT73C206 detects over-voltage by adaptor over-voltage detector, it stops charging and outputs over-voltage interrupt request flag (adpbir & adpir). thousandth of charge current is output from imoni pin. the resistor on imoni pin converts the charge current to voltage. this feature allows AT73C206 to monitor charge current through adc. 5.5.2 li-ion battery charger block diagram figure 5-14. li-ion battery charger block diagram charge regualtor charger control circuit charge current monitor adapter detector temperature detector over voltage detector ac adapter adpinb gndchg imoni chgout chgadp vddio vbat 1uf 2.7k ohm? rpc[2:0] chgonb tp[1:0] adpbiren/ adpiren adpbir/adpir to 8-bit adc rchgcnt to irq monitor li-ion battery 4.7uf table 5-22. pin description pin name function level chgadp power input pin for charger block (connected to ac adaptor) 5v chgout charge output pin (connected to battery) vbat imoni charge current monitor output (pull- down with external 2.7 kohm resistor) adpinb ac adaptor insertion detection output (o utput ?l? when ac adaptor inserted.) vddio 34 6329a?pmaac?12-aug-07 AT73C206 5.5.3 li-ion battery charger operation when ac adapter is connected, charge is asserted from charge off state. see (1) in figure 5-15 on page 35 . 5.5.3.1 charge off mode at charge off state, charge is disabled and charge current is 0ma. and, the power-on signal from charger block (chgpon) is ?l?. AT73C206 moves to trickle charge mode if: v chgadp > 4.6v and v chgadp 5.9v and chgonb bit = ?0" see (2) in figure 5-15 on page 35 . 5.5.3.2 trickle charge mode perform the trickle charge with 10% of the rapid charge current, which is register-programma- ble. the power-on signal from charger block (c hgpon) is ?l?. AT73C206 moves to rapid charge 1 mode with soft-start if: v chgout > 2.7v see (3) in figure 5-15 on page 35 . 5.5.3.3 rapid charge 1 mode rapid charge 1 current is register-programmable. the power-on signal from charger block (chg- pon) becomes ?h?. AT73C206 moves to trickle charge mode with soft-stop if: v chgout 2.6v see (4) in figure 5-15 on page 35 . also, over-temperature is detected by chip temperature detector, AT73C206 moves to rapid charge 2 with soft-stop. see (5) in figure 5-15 on page 35 . 5.5.3.4 rapid charge 2 mode perform the rapid charge 2 with 20% of rapid charge 1 current, which is register-programma- ble. the power-on signal from charger block (chgpon) is ?h?. when chip temperature falls, the charge current returns back to rapid charge mode 1 with soft-start. see (6) in figure 5-15 on page 35 . 5.5.3.5 any state AT73C206 moves to charge off mode if: v chgadp < 4.5v or v chgadp >6v or chgonb bit = ?1? see (7) in figure 5-15 on page 35 . AT73C206 monitors charge current with adc and disables charging by writing chgonb= ?1?. 35 6329a?pmaac?12-aug-07 AT73C206 5.5.4 li-ion battery charger state diagram figure 5-15. li-ion battery charger state diagram 5.5.5 li-ion battery charger chip temperature detection when rapid charge 1, if chip temperature approaches the die temperature, which is user selectable by register tp [1:0], AT73C206 reduces charge current to 20% of rapid charge 1 current. (rapid charge 2) when chip temperature falls, the charge current returns back to its full current. by repeating this process, AT73C206 is able to keep itself in temperature regulation. this feature not only pro- asynchronous from any state charge off charge current=0ma trickle charge 10% charge current rapid charge1 100% charge current v chgout Q 4.2v v chgadp > 4.6v and v chgadp < 5.9v and chgonb bit = 0 v chgout > 2.7v v chgout < 2.6v rapid charge2 2 0% charge current v chgout Q 4.2v high tempreature detected high tempreature released ac adapter connected v chgadp < 4.5v or v chgadp > 6v or chgonb bit = 1 chgpon=h chgpon=h chgpon=l chgpon=l adpinb=h adpinb=l v chgadp > 4.6v v chgadp < 4.5v soft-stop soft-start soft-start soft-stop 36 6329a?pmaac?12-aug-07 AT73C206 tects AT73C206 from overheating, but also allows higher charge current without risking damage to the system. soft-start/stop is used to minimize in-rush current on battery. figure 5-16. chip temperature detection and soft-start/stop 5.5.6 li-ion battery charger electrical characteristic s operating conditions (unless otherwise specified): vin= 3.6v, t a = 25 c, chgout=1uf. 100ma(20%) 50ma(10%) 500ma(100%) 3ms 3ms 3ms soft-start soft-start soft-stop i charge time start trickle charge start rapid 1charge 0 when AT73C206 detects over chip temperature, it gradually reduces charge current down to 20% (soft-stop). if the chip temperature falls, a73c206 gradually pulls charge current back to 100% (soft-start). table 5-23. li-ion battery charger electrical characteristics symbol parameter condition min typ max units v chgadp ac adapter operation voltage 4.5 6.3 v av det ac adapter detection voltage v chgadp , rising 4.6 v hysteresis 0.1 av ovlo ac adapter over voltage lock-out v chgadp , rising 6 v hysteresis 0.1 ci ss consumption current rapid charge = 500ma 3 ma charge off 1 v chg battery charge voltage i chgout = 0, t a = 0 to 85 c4.2v r imoni imoni resistor 2.7 k ? v imoni charge current monitor output r imoni =2.7k ? , i chgout = 850ma 2.295 v 37 6329a?pmaac?12-aug-07 AT73C206 ci rapid rapid charge current -12% 500 550 600 650 700 750 800 850 +12% ma ci tr i c k l e trickle charge current v chgout =2.2v, t a = 0 to 85 c percentage of ci rapid 51015% ct th chip temperature detection threshold 95 105 115 135 cv t transition voltage to rapid charge 1 mode v chgout , rising 2.7 v hysteresis 0.1 table 5-23. li-ion battery charger electrical characteristics 38 6329a?pmaac?12-aug-07 AT73C206 5.6 a/d converter the AT73C206 has an 8-bit a/d converter with 4 channels. input is selectable by register set: external pins an0 & an1 (common use with p0 and p1 pins of gpio), battery voltage monitor (batmon) and charge current monitor (imoni). input voltage ranges from 0v to vddio. generates the clock using rtc 32khz starts conversion by register set and inform the end of conversion to cpu through adcecir. the resistive voltage divider for battery voltage monitor is on/off controllable by register. buffer is on/off controllable by register. figure 5-17. adc block diagram 5.6.1 explanation of operation writing ?1? in adstart bit star ts conversion. adstart bit will be automatically cleared after conversion starts. after the c onversion is completed, AT73C206 sets adend bit and notices completion of conversion to cpu through irqb. the adend bit will be cleared by reading the converted data or by writing ?1? in adstart bit. and adcecir is cleared by writing ?0?. for re- conversion, write ?1? in adstart bit. changing adsel is prohibited during ad conversion. 8bit adc buf m u x p0/an0 p1/an1 imoni vin6 vddio control circuit raddata[7:0] radstart 32khz from rtc batmon adstart adend radccnt adiren adecir adecir adsel[1:0] btmen bufen 39 6329a?pmaac?12-aug-07 AT73C206 figure 5-18. adc timing diagram figure 5-19. adc internal operation sequence 5.6.2 electrical specification 5.6.2.1 a/d converter operating conditions (unless otherwise specified) vddio=2.5v or 2.8v or 3.0v, t a = 25 c. pow eron vo3 radend radcecir raddata[7:0] radstart reading addata clearing radcecir conversion data conversion time conversion time conversi o time radsel 2'h00 min 100us wait rbufen (rbtmen) table 5-24. a/d converter electrical characteristics symbol item condition min typ max units a/d converter adbit resolution 8bits inle integral nonlinearity error an(0,1) = 0 to vddio-0.1v -1 1 lsb dnle differential nonlinearity error a n(0,1) = 0 to vddio-0.1v -1 1 lsb input voltage range 0 vddio v conversion time 397 us 32khz adstart adend 12 34 5 12 adcecir sample point reading addata clearing radcecir 40 6329a?pmaac?12-aug-07 AT73C206 note: after conversion, a/d converter shifts to sleep mode automatically. iss supply current while converting 1 ma sleeping (note) 1 ua buffer iss supply current bufen=1 250 ua bufen=0 1 ua battery monitor ratio resistive voltage divider ratio 0.5 times rdiv resistive voltage divider 2 m table 5-24. a/d converter electrical characteristics 41 6329a?pmaac?12-aug-07 AT73C206 5.7 real time clock the real time clock provides the coin charge r egulator and 2 system of alarm function, which generate an interrupt on a set time. the accuracy of clock is dependant on the clock error off- set circuit. real time clock operates with 32.768 khz of external x?tal and capacitor. 5.7.1 features coin charge regulator built in with reverse-current protection diode counters for clock and calendar alarm function ? combination of day of the week, hour and minute ? combination of hour and minute only provides 32.768 khz clock output power-on flag, which recognizes that a power supplier turns on from 0v automatic definition for leap year is 2099, 12-hour or 24-hour format selectable high-accuracy of clock error offset circuit function alarm interrupts power on AT73C206 5.7.2 block diagram figure 5-20. rtc block diagram vin7 osc reg osc stop detector vddio rd rf 1sec timer xin xout 32khz clkstp out32k vsb coin battery rtc logic coin charge regulator rtcpon rtcctfgm rtcwafgm rtcdafgm rck32en 1k 42 6329a?pmaac?12-aug-07 AT73C206 5.7.3 power supply and charge of external coin battery when battery voltage over monitoring voltage the external coin battery performs charge with the regulated voltage applied from battery and, at the same time, this power is supplied to real time clock. 5.7.4 function of real time clock 1. clock function the clock and calendar in term of seconds, minutes, hours, day, month and below 2-digit-year are readable and writable via cpu. a low-order 2- digit-year that can be divided by 4 is defined as leap year. AT73C206 provides an automatic definition of leap year until 2099. 2. alarm function AT73C206 provides an alarm function, which generates interrupt signal for cpu on a pro- grammed time. there are 2 types of alarm; alarm_w and alarm_d. alarm_w can program a minute, hour and day of the week. single and mu ltiple day of the week are also programmable. however, alarm_d is minute and hour programmable. these two alarms are output from irqb pins. the cpu is allowed to check the status of each alarm by reading the corresponding regis- ter. 3. high-accuracy clock error offset circuit function oscillator circuit is configured by connecting an external x?ta l and capacitors (cg & cd). for accuracy of the clock, AT73C206 has the internal clock error offset circuit which keeps the clock precise by compensating the oscillator frequency drift with about 3 ppm (or about 1 ppm) step in range of 189 ppm (or about 63 ppm). (error 1.5 ppm (or 0.5 ppm) at 25 c after the compensation.) the compensation of freq uency in each system; enables high-accuracy of clock by using the x?tal which covers wide fluctuation. compensates a season-frequency-drift by correcting the clock error every season. enables high-accuracy of clock by correcting the clock error according to the temperature fluctuation. (this function is available only for the system with temperature detection function.) 4. constant cycle interrupt generation function in addition to alarm function, constant cycle inte rrupt is output through irqb pin. the cycle is selectable from 2 hz (1 time/0.5 sec.), 1 hz (1 time/1sec.), 1/60 hz (minute), 1/3600 hz (hour) and month (first day of each month). there are two types of output waveforms selectable in con- stant cycle; one is the waveform (2 hz, 1 hz) on normal pulse and the other is the one (every second, minute, hour and month), which is desi gned considering a cpu interrupt and a level interrupt. the status of register pin can be checked. 5. 32768 hz clock output oscillator frequency clock of x?tal units can be output through an out32k pin. the enable/dis- able of clock output is controllable by the ck32en bit. 6. power-on reset and oscilla tor stop detect ion function a. power-on reset function (pon flag) when the vsb power-supply pin rises from 0v, AT73C206 resets the control register and, simultaneously, allows cpu informed it by issu ing flag. this feature allows cpu to judge whether vsb power-supply pin has raised from 0v or it has been powe r-supplied by battery. 43 6329a?pmaac?12-aug-07 AT73C206 b. oscillator stop detection fu nction (osc stop detector) AT73C206 has a register, which remembers on/off of oscillator. this feature allows cpu judge whether oscilla tion has stopped. osc stop detector generates interrupt when it detects that the clock stops. enabling/dis- abling of the interrupt is selectable by stpire n bit in clkcnt register. also, the output of the osc stop detector can be read from the status monitor register. 5.7.5 electrical specification operating conditions (unless otherwise specified): vin = 3.6v, t a = 25 c. 5.7.6 structure of oscillation circuit figure 5-21. structure of oscillation circuit note: recommended external device: x?tal: fc-135 (epson ? ), (f: 32.768 khz), (r =70k ? max), cl = 9 pf cg, cd: 12 pf typ note: standard of internal device: rf: 20m ? typ rd: 100k ? typ note: oscillation circuit operates in internal voltage regulator. note: x?tal units: for x?tal units, use fc-135 (cl=9pf) of epson. c heck with the manu facturer about the value of crystal units in use. note: notes on mounting: place the crystal units as close as possible to the ic. do not place signal/power supply lines near the oscillation circuit. table 5-25. rtc electrical characteristics symbol parameter condition min. typ. max unit coin charge regulator ccrout vsb output voltage vin7=3.1 to 4.2v iout=0ua 2.943 3.050 3.157 v vf diode forward voltage iout = 1ma 0.75 v rtc vsbv oscillator operating voltage vin7=open 1.3 3.0 v tosc oscillation start time 1s osctor oscillation tolerance 5 times iss supply current 1.5 ua 32khz internal clock 32khz cg cd a xin xout rf rd oscreg vsb 44 6329a?pmaac?12-aug-07 AT73C206 make the insulation resistance between xin/xout pins and pcb board as high as possible. do not wire xin and xout in a long parallel line. condensation may stop the crystal oscillation or cause other errors. note: external input of clock (32.768 khz) to xin note: dc binding: forbidden due to the inconsistency with input level. note: ac binding: possible. however, oscillation stop detection is not assured, for error detection may occur due to the noise and other effects. note: do not operate other ic with oscillation output (xout output) in order to protect the stability of oscillation characteristics. 5.8 audio/voice 5.8.1 features voice codec: 16-bit linear codec (sampling frequency: 8 khz and 16 khz) audio dac: 16-bit linear stereo dac (sampling frequency: 48 khz to 8 khz) tone generator: supports 16 dtmf tones mono mic amplifier: differential amplifier stereo headphone amplifier: 22 mw (32 ohm load,thd+n=0.5%) mono receiver amplifier: 60 mw (32 ohm btl load,thd+n=1%) mono speaker amplifier: 300 mw (8 ohm btl load,thd+n=1%) microphone bias supply: output voltage=2.2v pll: reference clock=32.768 khz jack detect: input 200 kohm pull-up 5.8.2 block diagram power supply digital: 2.8v (vdd) analog: 2.8v(vddana) speaker amplifier: 3.6v[bat tery voltage level] (vbsp) receiver amplifier: 2.8v (vddhp) headphone amplifier: 2.8v (vddhp) pll: 2.8v (vddpll) 45 6329a?pmaac?12-aug-07 AT73C206 figure 5-22. codec block diagram note: the value of resistance must be determined depending on th e specification of the micropho ne which is used. when power ana- log codec (vddana), it is also required to supply power to digital codec (vdd). codec block voice adc voice dac audio dac lch audio dac rch micro phone micp micm spop spom hpol hpor micbias micbias serial interface avref vcom control interface vddpll vsspll acap vcap reference circuit delta-sigma modulator delta-sigma modulator decimation filter audio d/a converter tone/dtmf block delta-sigma modulator att att digital filter voice pll dout dsp i/f lrckio bckio din tone generator voice codec voice codec tone1 recop recom vddhp vsshp vbsp gndsp 8ohm 32ohm 32ohm 32ohm tone2 att att att vttnsw vrtnsw micdg(4:0) mute ,-10 to 20db 1db step recdg(4:0) mute,-30 to 0db 1db step tng1(3:0) -15 to 0db 1db step tng2(3:0) -15 to 0db 1db step lpf lpf lpf +6db +6db +0db +0db micag(3:0) 0 to 30db step 2db drvag(4:0) -40.5 to 6db step1.5db jkdeti jkdeto 200kohm tng3(2:0) -42 to 0db 6db step mixer lo ro aul aur vo volume fs=1.5vpp fs=2vpp fs=1.5vpp fs=1.5vpp freqsel(4:0) +0db mutedrv driver amp mutemic muteda delta-sigma modulator digital filter att att dattr(5:0) mute,- 62 to 0db 1db step dattl(5:0) mute,-62 to 0db 1db step micpon afs(2:0) apllsrc adivn/m(11:0) apllpon audio pll audio d/a converter vfs vpllsrc vdivn/m(11:0) vpllpon pll aformat(1:0) aclksel ifen side tone muteside sidedg(5:0) -62db to 0db 1db step tncon modeco(3:0) 1uf 1uf 1k (note) 1k (note) 47uf 47uf 0.1uf 0.1uf 1uf 0.1uf mux vasel din vlrcko vbcko abckio alrckio 0.1uf mutesmic smicbias smicpon vssana vddana 0.1uf smicbias 0.1uf smicp smicm 1uf 1uf 1k (note) micro phone 1k (note) ckin ckout from rtc 1 msec x4 deglitch interrupt 46 6329a?pmaac?12-aug-07 AT73C206 5.8.3 voice codec 16-bit linear codec sampling frequency: 8 khz and 16 khz interface: iis data format: linear transmit channel: 1ch inputs: 2ch (micp/micm, smicp/smicm) outputs: receiver, stereo headphone, speaker internal tone generator: dtmf/single tone mode: master level diagram: analog input=2.0vpp -> dout output=3.17dbm0 din input=0dbfs -> an alog output=1.5vpp tone data mix function: mix of tone data and voice data is controlled by register set attenuator: tx system: mute, -10db to 20db / 1db step rx system: mute, -30db to 0db / 1db step side tone: loop-back of tx side to rx side (mute,-62db to 0db) smoothing gain control: gain changes to the current set value by smoothing gain control at 1db/fs ? available in tx system, rx system and side tone 5.8.4 audio dac dac: 16-bit linear stereo dac sampling frequency: 48 khz, 44.1 khz, 32 khz, 24 khz, 22.05 khz, 16 khz, 11.025 khz, 8 khz interface data format: iis, ljf, rjf interface mode: master and slave level diagram: din input=3.17dbm0 -> analog output=1.5vpp outputs: receiver, stereo headphone, speaker attenuator: mute,-62db to 0db / 1db step smoothing gain control: gain changes to the current set value by smoothing gain control at 1db/fs available in lch and rch 5.8.5 tone generator 16 dtmf tones: dtmf low tone is 697,770, 852 or 941hz. ? dtmf high tone is 1209,1336, 1477 or 1633hz. 2 programmable tones: from 0hz to 3992.1875hz ? frequency of programmable tone1/2 = 7.8125hz x ptn1/2 can be generated independently software start: writing the register (tncon bit) via spi starts tone generating hardware stop: internal programmable hardware timer stops tone generating. the range of the time is from 80ms to 200ms (default 100ms) 47 6329a?pmaac?12-aug-07 AT73C206 gain control: gains of tone1 and tone2 in tone generator are individually settable. after mixing tone1 and tone2, the gain of tone3 is settable. 5.8.6 analog control mode control: driver amp (receive r amp/ speaker amp/ headphone amp) ? power-down / stand-by ? mono/ stereo mute control: micamp, smicamp mute ? driver amplifier mute gain control: mic-gain: 0 to 30db/ step 2db driver-gain ?40.5 to 6db/ step 1.5db 5.8.7 micbias, smicbias micbias and smicbias consist of power supply, error am plifier, driver transistor and resistor set for output voltage setting. on/off of micbias and smicbias is controllable by register set. the regulator has an internal sink transistor. figure 5-23. micbias, smicbias 5.8.8 pll there are two types of pll: pll for voice codec and pll for audio dac. it provides the clock corresponding to the register-set sampling frequency by regulating the reference clock.power down control of pll for voice codec and pll for audio dac can be operated independently. when power down control of pll for voice is set, digital voice codec block also goes to power- down mode. when power down control of pll for audio is set, digital audio dac block also goes power- down mode. vddana micbias 1:on 0:off micpon nchtr vssana micbias vref 0.1uf (smicpon) (smicbias) (smicbias) 48 6329a?pmaac?12-aug-07 AT73C206 5.8.9 jack detector AT73C206 integrates an input port (with 200 kohm of pull-up resistor) and an output port for detecting headset insertio n. the detection signal will be output through the output port after per- form chattering rejection (1ms x 4). when the insertion/removal of the headset jack is detected, AT73C206 will generate an in terrupt. permit/prohibit of the inte rrupt is controllable by register. 5.8.10 interface timing data format 5.8.10.1 voice interface timing figure 5-24. voice interface timing operating conditions (unless otherwise specified): vdd=2.8v, t a = 25 c, fs:16 khz, 8 khz note: fs: 16khz, 8khz table 5-26. voice interface electrical characteristics parameter condition min typ max unit bckio frequency tbclk 32* fs khz lrckio delay time tblr bckio falling -10 100 ns din setup time tads bckio rising 50 ns din hold time tadh bckio rising 50 ns dout delay time tbado bckio falling - 50 ns lrc ki o bckio di n dout tb a d o ta d h ta d s tb l r ? ? ? ? ? ? ? ? ? ? ? ? 49 6329a?pmaac?12-aug-07 AT73C206 5.8.10.2 voice interface data format linear 50 6329a?pmaac?12-aug-07 AT73C206 5.8.10.3 audio interface timing - slave and master modes figure 5-27. audio interface timing (slave mode) operating conditions (unless otherwise specified) vdd =2.8v, t a = 25 c. note: fs: 48 khz, 44.1 khz, 32 khz, 24 khz, 22.05 khz, 16 khz, 11.025 khz, 8 khz figure 5-28. audio interface timing (master mode) operating conditions (unless otherwise specified): vdd=2.8v t a = 25 c. note: fs: 48 khz, 44.1 khz, 32 khz, 24 khz, 22.05 khz, 16 khz, 11.025 khz, 8 khz table 5-27. audio interface (slave mode) electrical characteristic s parameter conditions min typ max unit bckio frequency tbclk 32*fs 64*fs khz lrclko delay time tblr bckio falling -100 100 ns din setup time tads bckio rising 50 ns din hold time tadh bckio rising 50 ns table 5-28. audio interface (master mode) electrical characteristics parameter conditions min typ max unit bckio frequency tbclk 64*fs khz lrckio delay time tblr bckio falling -10 100 ns din setup time tads bckio rising 50 ns din hold time tadh bckio rising 50 ns lrckio bckio din tblr tads tadh lrckio bckio din tblr tads tadh 51 6329a?pmaac?12-aug-07 AT73C206 5.8.10.4 audio interface format - iis, left justify, right justify figure 5-29. audio interface format - iis figure 5-30. audio interface format - left justify format figure 5-31. audio interface format - right justify format where: lrckio: audio interface l/r select input/output bckio: audio interface serial bit clock input/output din: audio interface serial data input note: input/output mode of lrckio and bckio pins is c ontrollable by register set. (slave mode/master mode) lrckio bckio din lch rch d15 d14 d1 d0 d15 d14 d1 d0 lrckio bckio din lch rch d15 d14 d1 d0 d15 d14 d1 d0 lrckio bckio din lch rch d15 d14 d1 d0 d15 d14 d1 d0 d1 d0 52 6329a?pmaac?12-aug-07 AT73C206 5.8.11 audio electrical characteristics operating conditions (unless otherwise specified) : vdd=2.8v, vddana = 2.8v, vbsp=3.6v, vddhp=2.8v, vddpll=2.8v, t a = 25 c. table 5-29. electrical characteristics parameter conditions min typ max units comment digital power supply current audio playback mode, fs=48khz 12 15 ma analog power supply quiescent current no load, no signal 12 15 ma speaker driver quiescent current no load, no signal 3 6 ma digital power down current 1.0 5 ua analog power down current 0.5 3 ua micamp input impedance 60 kohm headphone amplifier output power thd+n = 0.5%, fout = 1khz rl=32 ohm 22 mw mono receiver amplifier output power thd+n = 1%, fout = 1khz rl=32 ohm 60 mw mono speaker amplifier output power thd+n = 1%, fout = 1khz rl=8ohm 300 mw headphone amplifier total harmonic distortion + noise1 fin = 1khz, pout = 16 mw rl=32 ohm audio dac path 0.01 % mono receiver amplifier to t a l harmonic distortion + noise fin = 1khz, pout = 40 mw rl=32 ohm audio dac path 0.01 % mono speaker amplifier to t a l harmonic distortion + noise fin = 1khz, pout = 200 mw rl=8 ohm 0.2 % signal-to-noise ratio (voice playback path) signal=0dbfs@1 khz; noise=digital zero, a-weighted; 0db gain setting fs = 8khz 85 db signal-to-noise ratio (audio playback path) signal=0dbfs@1 khz; stereo load; noise=digital zero, a-weighted; 0db gain setting 90 db dynamic range (voice playback path) signal=-60dbfs@1 khz; stereo load; a-weighted; 0db gain setting fs = 8 khz 85 db dynamic range (audio playback path) signal=-60dbfs@1 khz; stereo load; a-weighted; 0db gain setting fs = 44.1khz 90 db 53 6329a?pmaac?12-aug-07 AT73C206 note: conditions of dynamic range: + 60db sinad at ?60db fs digital input. signal-to-noise ratio (voice adc path) reference signal = 0dbfs; micp, micm terminated with 2uf to ground; 20 db micamp gain setting fs = 8 khz 75 db dynamic range (voice adc path) micp, micm terminated with signal=-60dbfs@1 khz 0db mic preamp gain setting fs = 8 khz 75 db stereo channel-to-channel crosstalk fs=44.1 khz, fin=1 khz sine wave at ?3dbfs -75 db maximum voltage differential mic input voltage 0db mic preamp gain setting 2 vp-p micbias output voltage 10ua iout ioutmax 2.1 2.2 2.3 v table 5-29. electrical characteristics parameter conditions min typ max units comment 54 6329a?pmaac?12-aug-07 AT73C206 5.8.11.1 voice adc codec electrical characteristics operating conditions (unless otherwi se specified) vdd=2. 8v, vddana = 2.8v, vb sp=3.6v, vddhp=2.8v, vddpll=2.8v, t a = 25 c. table 5-30. voice adc electrical characteristics parameter conditions min typ max unit comment absolute gain 0dbm0@1020hz, gain=0db -1 1 db gain tracking -10dbm0@1020hz 3dbm0 to 40dbm0 -0.3 0.3 db -40dbm0 to 55dbm0 -0.5 0.5 db s/n 8khz: c-message 1020hz, analog gain=0db 3dbm0 73 83 db thd+n bw= c-message 1020hz, analog gain=0db 3dbm0 -50 -40 db 0dbm0 -50 -40 db -5dbm0 -60 -50 db -10dbm0 -60 -50 db -20dbm0 -50 -40 db -30dbm0 -45 -35 db -40dbm0 -40 -30 db speech delay 0.5 ms idle channel noise8khz:c- message analog gain=0db -86 dbv 55 6329a?pmaac?12-aug-07 AT73C206 5.8.11.2 voice dac codec electrical characteristics operating conditions (unless otherwi se specified) vdd=2. 8v, vddana = 2.8v, vb sp=3.6v, vddhp=2.8v, vddpll=2.8v, t a = 25 c. table 5-31. voice dac electrical characteristics parameter conditions min typ max unit comment absolute gain 0dbm0@1020hz, gain=0db -1 1 db gain tracking -10dbm0@1020hz, gain=0db 3dbm0 to 40dbm0 -0.3 0.3 db -40dbm0 to 55dbm0 -0.5 0.5 db s/n hpol output 8khz: c-message 1020hz, gain=0db 3dbm0 73 83 db thd+n hpol output 8khz:c-message 1020hz, gain=0db 3dbm0 -60 -50 db 0dbm0 -60 -50 db -5dbm0 -70 -60 db -10dbm0 -70 -60 db -20dbm0 -60 -50 db -30dbm0 -50 -40 db -40dbm0 -40 -30 db speech delay 0.5 ms idle channel noise 8khz:c-message hpol output -90 dbv 56 6329a?pmaac?12-aug-07 AT73C206 5.8.11.3 audio dac electrical characteristics operating conditions (unl ess otherwise specified): vdd=2.8v, vddana=2.8v, vbsp=3.6v, vddhp=2.8v, vddpll=2.8v, t a = 25 c, gain:0db, fs =44.1khz operating conditions (unless otherwi se specified) vdd=2. 8v, vddana = 2.8v, vb sp=3.6v, vddhp=2.8v, vddpll=2.8v, t a = 25 c. table 5-32. audio dac electrical characteristics parameter conditions min typ max unit comment absolute gain -3dbfs@1020hz, gain=0db -1 1 db gain tracking -10dbfs@1020hz 0dbfs to 35dbfs -0.3 0.3 db -35dbfs to 50dbfs -0.5 0.5 db s/n 0dbfs@1020hz 84 90 a-weight db thd+n gain=0db -80 -70 0dbfs@1020hz bw=20hz to 20khz crosstalk -75 db table 5-33. audio dac digital filter electrical characteristics parameter conditions min typ max unit comment pass band 0.445 fs pass band ripple 0fs to 0.445 fs -0.3 0 0.3 db stop band 0.555 fs stop band attenuation 0.555 fs to 1 fs -50 db 48/44.1/32khz stop band attenuation 0.555 fs to 1 fs -75 db 24/22.05/16/11.025/8 khz 57 6329a?pmaac?12-aug-07 AT73C206 5.8.11.4 tone generator electrical characteristics operating conditions (unless otherwi se specified) vdd=2. 8v, vddana = 2.8v, vb sp=3.6v, vddhp=2.8v, vddpll=2.8v, t a = 25 c. 5.8.11.5 micbias, smicbias electrical characteristics operating conditions (unless otherwi se specified) vdd=2. 8v, vddana = 2.8v, vb sp=3.6v, vddhp=2.8v, vddpll=2.8v, ta = 25 c. table 5-34. tone generator electric al characteristics parameter conditions min typ max unit comment signal output level gain=0db setting 3.17 dbm0 frequency deviation 50hz to 3.4khz -2 2 hz thd+n hpol(tonegain=0db) -40 db table 5-35. mic(smic)bias electrical characteristics symbol parameter conditions min typ max unit vout output voltage 10ua iout ioutmax 2.1 2.2 2.3 v iout output current 1ma iss consumption current on operation-mode iout=0ma 200 ua istnby consumption current on off-mode micbias on off-mode 0.01 1 ua rr ripple rejection rate 2.8v+0.1vp-p iout=ioutmax/2=217hz 65 db vout/ topt output voltage temperature efficiency -30 c ta 85 c 100 ppm/ en output noise level bw=20hz to 6.6khz(with c-message), iout=ioutmax/2 10 uvrms tu rise time cout=0.1uf, iout=ioutmax, vout > 90% 100 us td fall time cout=0.1uf, iout=0ma, vout < 0.5v 500 us 58 6329a?pmaac?12-aug-07 AT73C206 5.8.12 clk voice pll generates the clock for voice block. audio pll generates the clock for audio block. 5.8.12.1 block diagram figure 5-32. clock block diagram figure 5-33. pll block diagram pll audio block pll voice block rvpllpon rapllpon 32.768khz select rvpllsrc 32.768khz select divide factor divide factor voice pll audio pll rapllsrc rafs osc xin xout 32.768khz ckin ckin powerdown powerdown 32.768khz div/mux ckout ckin 32.768khz voice pll audio pll vcap acap generated clock for voice generated clock for audio 59 6329a?pmaac?12-aug-07 AT73C206 5.8.13 voice pll the internally generated clock frequency for voice pll should be: fv=53.248mhz. if input clock=xin (when xin selected, it is automatically multiplied by 1625.) the internally generated clock fv= 32.768khz x 1625=53.248mhz. if input clock = ckin, the internally generated clock can be calculated by: example: if ckin=26 mhz, 5.8.14 audio pll the internally generated clock frequency for audio pll should be: f a = fs x 512 if input clock = xin (when xin selected, it is automatically multiplied by afs bit value). note: ma = adivm + 1, na = adivn + 1 if input clock=ckin (this does not exist in afs bit.) example: if ckin = 26mhz: note: set each register value considering the relation between the main system clock and audio codec clock when the audio codec clock needs to synchronize with the main system clock. note: sampling rate setting: when using ckin for input clock, set nv(na) at ckin nv(na) > 30 khz. fv=ckin x nv mv (mv= vdivm +1, nv=vdivn+1) fv=26mhz x 125 256 = 53.248mhz table 5-36. audio pll (input clock = xin) fs (khz) na ma internally generated f a (mhz) 48 1 750 24.576 44.1 1 689 22.577152 32 1 500 16.384 table 5-37. audio pll (input clock = ckin) fs (khz) na ma internally generated f a (mhz) 48 347 328 24.576369 44.1 114 99 22.578947 32 411 259 16.384428 f a =ckin x na ma 60 6329a?pmaac?12-aug-07 AT73C206 5.8.15 clock output function each clock can be output through ckout pin. the output clock is selectable by ckosel bit. figure 5-34. clock output diagram 5.8.16 pll 5.8.16.1 audio pll/voice pll electrical characteristics: vddpll=2.8v, t a = 25 c. m u x ckout 32.768khz div. f a ckosel[2:0] table 5-38. pll electrical characteristics parameter conditions min typ max unit comment input frequency ckin pin 0.1 30 mhz xin pin 32.768 khz output jitter short term, 200 ps no impact on audio dac output duty cycle 40 50 60 % no impact on audio dac lock time 5 10 ms supply current (voice) input clock = 19.2 mhz 1 3 ma supply current (audio) input clock = 19.2 mhz 1 ma 61 6329a?pmaac?12-aug-07 AT73C206 5.9 keypad led keyled driver has nch ope n-drain type large curr ent output pin. and, the led on/off is con- trollable by register set and the brightness is settable by external current control resistor 5.9.1 block diagram figure 5-35. keypad led driver block diagram 5.9.2 explanation of operation keyled on/off is controllable by kleden bit. when kleden bit is ?1?, keyled is enabled. 5.9.3 electrical characteristics vin=3.6v, t a = 25 c. kleden vin keyled keypad led gndkey table 5-39. keypad led driver pin description pin name i/o function keyled o keyled driver gndkey g gnd only for keyled driver table 5-40. keypad led driver elec trical characteristics symbol parameter condi tion min typ max unit vol output voltage ?l? level iout = -100 ma 0.5 v ioz output off leakage vin=04.2v 1 ua 62 6329a?pmaac?12-aug-07 AT73C206 5.10 general purpose i/o AT73C206 supports 4-channel gpio. all gpio input/output are controlled by register configure independently. 5.10.1 block diagram figure 5-36. general purpose io block diagram 5.10.2 explanation of operation the gpio has 4-channel i/o function. with pin control, it is possible to control input or output setting of each channel individually. when it is set in output modegpiodir= ?1?, the output data, which is written in gposet register, is output. when it is set in input mode gpiodir= ?0?, the pin level is readable from gpimon register. i/o voltage varies by vddio voltage. set gpain= ?0? when connect analog signal to p0/an0 and p1/an1. then, gpiodir becomes invalid and gpio starts operat ing in analog input mode. and, the gpimoni will be set to ?0?. gposet[1:0] gpimon[1:0] gpiodir[1:0] vddio oeb gpain[1:0] p0/an0 p1/an1 gposet[3:2] gpimon[3:2] gpiodir[3:2] vddio oeb p2 p3 to adc block 63 6329a?pmaac?12-aug-07 AT73C206 note: 1. hi-z is prohibited. table 5-41. gpio truth table setting register gpio terminal reading register gpain gpiodir gposet gpimon 0 (analog input mode) don?t care don?t care analog signal input -> adc 8-bit l 1 1 (output mode) 1h1 0l0 0 (input mode) don?t care h1 l0 hi-z (1) x 64 6329a?pmaac?12-aug-07 AT73C206 5.11 irq monitor with irq monitor, AT73C206 can read all the permitted interrupt request flags coming from dif- ferent functional blocks when interrupt occurred, cpu is informed it by asserting irqb and read register rirqmon reg- ister to identify which block is producing the interrupt. the rirqmon is read only register. nor gate signal of each perm itted interrupt request flag s will be output from irqb. figure 5-37. irq monitor block diagram adcec ir ctfg rirqmon irqb wafg dafg jackbir jackir adpbir adpir stpir jkbiren jkiren adpbiren adpiren stpiren adc iren wale dale jackbirm jackirm adpbirm adpirm stpirm adcec irm ctfgm wafgm dafgm ct[2:0] 65 6329a?pmaac?12-aug-07 AT73C206 5.12 cpu interface AT73C206 employs a synchronous spi for interfacing to cpu. 5.12.1 sen and data read write timing AT73C206 interfaces with cpu using 4 signal lines. sdi is data input (write) from cpu and sdo is data output (re ad) to cpu. sclk is synchronous cl ock and cpu outputs data at falling edge of sclk and inputs at rising edge of sclk . AT73C206 cpu interface consists of address decoder, address latch, shift register, control circuit and clock counter. refer to the diagram below. figure 5-38. cpu interface configuration 5.12.2 data transmission format an ?h? to ?l? transition on sen line asserts data transmission and an ?l? to ?h? transition deas- serts data transmission. the data is transmitted by byte. the first 7 bits contains register address and the last bit determine s read or write. when writin g mode, the following 1 byte will be the data. when read mode, the following 8-bit is ignored and an appointed address data (8- bit) is output from sdo pin. cpu needs to deassert sen everytime after read and write data. figure 5-39. writing data shift register clock counter address latch address decoder ce wdata[7:0] wb register block rdata[7:0] shift register sdi sdo sclk sen control circuit writing data sen sclk a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sdi sdo 0 hi-z hi-z 66 6329a?pmaac?12-aug-07 AT73C206 figure 5-40. reading data 5.12.3 target electrical characteristics ac characteristics: ta = -30 c to 85 c d0 reading data sen a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 sdi sdo don't care 1 sclk hi-z hi-z table 5-42. ac characteristics symbol parameter min typ max units tcymc clk cycle time 100 ns twhmc clk cycle high interval 50 ns twlmc clk cycle low interval 50 ns trmc clk rise time 20 ns tfmc clk fall time 20 ns tws write data setup time 20 ns twh write data hold time 10 ns trd read data delay time 25 ns trh read data hold time 0 ns tdre read data output enable delay time 25 ns tdrd read data output disable delay time 25 ns tses time from sen ?h? to a sck input 50 ns tseh sen ?h? hold time 100 ns tsel sen minimum ?l? time 100 ns 67 6329a?pmaac?12-aug-07 AT73C206 figure 5-41. cpu interface timing chart tcymc twhmc trmc tfmc twlmc sclk sdi a7 tws twh sen tses tseh d0 sclk sdo trd trh sen tdre d7 tdrd a5 a0 tsel 68 6329a?pmaac?12-aug-07 AT73C206 6. registers name address register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ldo 00 ldoen r/w - ldo10on ldo9on ldo8o n ldo7on ldo6on ldo5on ldo4on 01 ldo1cnt r/w opmodev - - opmode1 - - ldo1dac[1] ldo1dac[0] 02 ldo3cnt r/w resdet dac[1] resdet dac[0] - opmode3 - - ldo3dac[1] ldo3dac[0] 03 ldo4cnt r/w - - - - - - ldo4dac[1] ldo4dac[0] 04 ldo5cnt r/w - - - - - - ldo5dac[1] ldo5dac[0] 05 ldo8cnt r/w - - - - - - - ldo8sel white led driver 06 ledcnt r/w d7 d6 d5 d4 d3 d2 d1 d0 charger 07 chgcnt1 r/w - - tp[1] tp[0] rpc[2] rpc[1] rpc[0] chgonb 08 chgcnt2 r/w - - - - adpbiren adpiren adpbir adpir adc 09 adccnt r/w - - bufen btmen adcecir adciren adsel[1] adsel[0] 0a adstart r/w - - - - - - adend adstart 0b adcdata r addata[7] addata[6] addata[5] addata[4] addata[3] addata[2] addata[1] addata[0] keypad led 0c kled r/w - - - - - - - kleden clk 0d clkcnt r/w - - - - - stpiren stpclkir ck32en irq 0e irqmon1 r - - - - jackbirm jackirm adpbirm adpirm 0f irqmon2 r - - - clkstpm adcecirm ctfgm wafgm dafgm rtc 10 sec r/w - s40 s20 s10 s8 s4 s2 s1 11 min r/w - m40 m20 m10 m8 m4 m2 m1 12 hour r/w - - h20pa h10 h8 h4 h2 h1 13 week r/w - - - - - w4 w2 w1 14 day r/w - - d20 d10 d8 d4 d2 d1 15 month r/w - - - mo10 mo8 mo4 mo2 mo1 16 year r/w y80 y40 y20 y10 y8 y4 y2 y1 17 rtcadj r/w - f6 f5 f4 f3 f2 f1 f0 18 wal_min r/w - wm40 wm20 wm10 wm8 wm4 wm2 wm1 19 wal_hour r/w - - wh20pa wh10 wh8 wh4 wh2 wh1 1a wal_week r/w - ww6 ww5 ww4 ww3 ww2 ww1 ww0 1b dal_min r/w - dm40 dm20 dm10 dm8 dm4 dm2 dm1 1c dal_hour r/w - - dh20pa dh10 dh8 dh4 dh2 dh1 1d - - - - - - - - - - 1e rtccnt1 r/w wale dale z1224 scra test ct2 ct1 ct0 1f rtccnt2 r/w - xstz pon scrb ctfg wafg dafg 69 6329a?pmaac?12-aug-07 AT73C206 addres s register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 audio/voice 20 pwrcnt r/w - - smicpon micpon - - dauon dvoon 21 vmode r/w vasel mssel ifen vfs - - - vformat 22 amode r/w - afs[2] afs[1] afs[0] - - aformat[ 1] aformat[ 0] 23omoder/w---- modeco[3 ] modeco[2 ] modeco[1 ] modeco[0 ] 24 mute r/w - - muteda muteside - mutedrv mutesmic mutemic 25 drvag r/w - - - drvag[4] drvag[3] drvag[2] drvag[1] drvag[0] 26 micag r/w - - - - micag[3] micag[2] micag[1] micag[0] 27 micdg r/w - - - micdg[4] micdg[3] micdg[2] micdg[1] micdg[0] 28reservedr/w-------- 29reservedr/w-------- 2a sidedg r/w - - sidedg[5] sidedg[4] sidedg[3] sidedg[2] sidedg[1] sidedg[0] 2b recdg r/w - - - recdg[4] recdg[3] recdg[2] recdg[1] recdg[0] 2c dattl r/w - - dattl[5] dattl[4] dattl[3] dattl[2] dattl[1] dattl[0] 2d dattr r/w - - dattr[5] dattr[4] dattr[3] dattr[2] dattr[1] dattr[0] 2ereservedr/w-------- 2f tncnt r/w tncon vrtnsw vttnsw - tntime[3] tntime[2] tntime[1] tntime[0] 30 tnset r/w tng3[2] tng3[1] tng3[0] freqsel[4 ] freqsel[3 ] freqsel[2 ] freqsel[1 ] freqsel[0 ] 31 tngain r/w tng2[3] tng2[2] tng2[1] tng2[0] tng1[3] tng1[2] tng1[1] tng1[0] 32 ptn1setl r/w ptn1[7] ptn1[6] ptn1[5] ptn1[4] ptn1[3] ptn1[2] ptn1[1] ptn1[0] 33ptn1sethr/w-------ptn1[8] 34 ptn2setl r/w ptn2[7] ptn2[6] ptn2[5] ptn2[4] ptn2[3] ptn2[2] ptn2[1] ptn2[0] 35ptn2sethr/w-------ptn2[8] 36 apllcnt r/w apllpon ckosel[2] ckosel[1] ckosel[0] - - - apllsrc 37 vpllcnt r/w vpllpon - - - - - - vpllsrc 38 adivnl r/w adivn[7] adivn[6] adivn[5] adivn[4] adivn[3] adivn[2] adivn[1] adivn[0] 39 adivnh r/w - - - - adivn[11] adivn[10] adivn[9] adivn[8] 3a adivml r/w adivm[7] adivm[6] adivm[5] adivm[4] adivm[3] adivm[2] adivm[1] adivm[0] 3b adivmh r/w - - - - adivm[11] adivm[10] adivm[9] adivm[8] 3c vdivnl r/w vdivn[7] vdivn[6] vdivn[5] vdivn[4] vdivn[3] vdivn[2] vdivn[1] vdivn[0] 3d vdivnh r/w - - - - vdivn[11] vdivn[10] vdivn[9] vdivn[8] 3e vdivml r/w vdivm[7] vdivm[6] vdivm[5] vdivm[4] vdivm[3] vdivm[2] vdivm[1] vdivm[0] 3f vdivmh r/w - - - - vdivm[11] vdivm[10] vdivm[9] vdivm[8] status40stmonr-----jackmon clkstpmo n onswmon 70 6329a?pmaac?12-aug-07 AT73C206 notes: 1. don?t set ?1? to reserved bits. 2. don?t write ?1? or ?0? to undefined registers. 3. the registers 07h08h are power supplied fr om chgadp. when not connected to ac a daptor, these registers(07h08h)will be cleared. 4. the registers 10h1fh are power supplied from vsb. when there is no sub-battery, these registers(10h1fh ) will be cleared. 5. the registers 20h3fh are power supplied from vdd. if turn off ldo10, registers 20h3fh will be cleared. at this time, writing in these registers will not be available. 6.1 regulators registers 6.1.1 ldoen: ldos output control register (address 00h) gpio 41 gpiodir r/w - - gpain1 gpain0 gpiodir3 gpiodir2 gpiodir1 gpiodir0 42 gposet r/w - - - - gposet3 gposet2 gposet1 gposet0 43 gpimon r - - - - gpimon3 gpimon2 gpimon1 gpimon0 jack 44 jackcnt r/w - - - - jkbiren jkiren jackbir jackir bit symbol r/w function 1 0 initial value gsp=l gsp=h 7 ----- ----- reserved ----- ----- ----- ----- 6 ldo10on r/w ldo10 on/off control bit on off 0 0 5 ldo9on r/w ldo9 on/off control bit on off 0 0 4 ldo8on r/w ldo8 on/off control bit on off 0 1 3 ldo7on r/w ldo7 on/off control bit on off 1 0 2 ldo6on r/w ldo6 on/off control bit on off 1 1 1 ldo5on r/w ldo5 on/off control bit on off 0 1 0 ldo4on r/w ldo4 on/off control bit on off 0 0 71 6329a?pmaac?12-aug-07 AT73C206 6.1.2 ldo1cnt: ldo1 control register (address 01h) note: the initial value is selectable by ldo1sel pin. vref eco-mode (opmodev= ?1?) is settable only when ldo1 and ldo3 are in eco-mode (opmode1, opmode3) and ldo4~10 are disabled. in other case, set it in normal-mode (opmodev= ?0?). bit symbol r/w function 1 0 initial value 7 opmodev r/w vref eco/normal control bit eco mode normal mode 0 6-5 ----- ----- reserved ----- ----- ----- 4 opmode1 r/w ldo1 eco/normal control bit eco mode normal mode 0 3-2 ----- ----- reserved ----- ----- ----- 1-0 ldo1dac[1:0] r/w setting the output voltage to ld o1 see the ldo1 output voltage table below (note) output voltage for ldo1 ldo1dac [1:0] output voltage 11 1.5v 10 1.3v 01 1.0v 00 0.9v initial value se lect for ldo1 ldo1sel ldo1dac initial value h11 l10 72 6329a?pmaac?12-aug-07 AT73C206 6.1.3 ldo3cnt: ldo3 control register (address 02h) bit symbol r/w function 1 0 initial value gsp=l gsp=h 7-6 resdetdac[1:0] r/w setting the resdet voltage as below 00 01 5 ----- ----- reserved ----- ----- ----- 4 opmode3 r/w ldo3 eco/normal control bit eco mode normal mode 0 3-2 ----- ----- reserved ----- ----- ----- 1-0 ldo3dac[1:0] r/w setting the output voltage to ldo3 as below 00 01 resdet detection voltage resdetdac [1:0] detection voltage 11 ----- 10 for 3.0v 01 for 2.8v 00 for 2.5v output voltage of ldo3 ldo3dac [1:0] output voltage 11 ----- 10 3.0v 01 2.8v 00 2.5v 73 6329a?pmaac?12-aug-07 AT73C206 6.1.4 ldo4cnt: ldo4 control register (address 03h) bit symbol r/w function 1 0 initial value 7-2 ----- ----- reserved ----- ----- ----- 1-0 ldo4dac[1:0] r/w setting the output voltage to ldo4 as below 00 output voltage of ldo4 ldo4dac [1:0] output voltage 11 3.1v 10 3.0v 01 2.8v 00 1.8v 74 6329a?pmaac?12-aug-07 AT73C206 6.1.5 ldo5cnt: ldo5 control register (address 04h) 6.1.6 ldo8cnt: ldo8 control register (address 05h) bit symbol r/w function 1 0 initial value gsp=l gsp=h 7-2 ----- ----- reserved ----- ----- ----- ----- 1-0 ldo5dac[1:0] r/w setting the out put voltage to ldo5 as below 10 01 output voltage of ldo5 ldo5dac [1:0] output voltage 11 3.3v 10 3.0v 01 2.8v 00 2.7v bit symbol r/w function 1 0 initial value gsp=l gsp=h 7-1 ----- ----- reserved ----- ----- ----- ----- 0 ldo8sel r/w setting the output voltage to ldo8 2.8v 1.8v 0 1 75 6329a?pmaac?12-aug-07 AT73C206 6.2 white led driver register 6.2.1 ledcnt: white led brightness (address 06h) each sink current of din1-4 can be set by the code of d4-d0. defaults shown in bold . led current (ma) data charge pump white led d7 d6 d5 d4 d3 d2 d1 d0 25.0 ----- ----- ----- 1 1 1 1 1 on 24.2 ----- ----- ----- 1 1 1 1 0 on 23.4 ----- ----- ----- 1 1 1 0 1 on 22.6 ----- ----- ----- 1 1 1 0 0 on 21.8 ----- ----- ----- 1 1 0 1 1 on 21.0 ----- ----- ----- 1 1 0 1 0 on 20.2 ----- ----- ----- 1 1 0 0 1 on 19.4 ----- ----- ----- 1 1 0 0 0 on 18.5 ----- ----- ----- 1 0 1 1 1 on 17.7 ----- ----- ----- 1 0 1 1 0 on 16.9 ----- ----- ----- 1 0 1 0 1 on 16.1 ----- ----- ----- 1 0 1 0 0 on 15.3 ----- ----- ----- 1 0 0 1 1 on 14.5 ----- ----- ----- 1 0 0 1 0 on 13.7 ----- ----- ----- 1 0 0 0 1 on 12.9 ----- ----- ----- 1 0 0 0 0 on 12.1 ----- ----- ----- 0 1 1 1 1 on 11.3 ----- ----- ----- 0 1 1 1 0 on 10.5 ----- ----- ----- 0 1 1 0 1 on 9.7 ----- ----- ----- 0 1 1 0 0 on 8.9 ----- ----- ----- 0 1 0 1 1 on 8.1 ----- ----- ----- 0 1 0 1 0 on 7.3 ----- ----- ----- 0 1 0 0 1 on 6.5 ----- ----- ----- 0 1 0 0 0 on 5.6 ----- ----- ----- 0 0 1 1 1 on 4.8 ----- ----- ----- 0 0 1 1 0 on 4.0 ----- ----- ----- 0 0 1 0 1 on 3.2 ----- ----- ----- 0 0 1 0 0 on 2.4 ----- ----- ----- 0 0 0 1 1 on 1.6 ----- ----- ----- 0 0 0 1 0 on 0.8 ----- ----- ----- 0 0 0 0 1 on off ----- ----- ----- 0 0 0 0 0 off 76 6329a?pmaac?12-aug-07 AT73C206 6.3 charger control registers 6.3.1 chgcnt1 : charger control register1 (address 07h) tp1, tp0 (bit5, 4) [w]: chip temperature detection threshold select bits rpc [2:0] (bit3, 2, 1) [w]: rapid charge current select bits 6.3.2 chgcnt2 : charger control register2 (address 08h) bit name r/w function 1 0 initial value 7-6 ----- ----- reserved ----- ----- ----- 5-4 tp[1:0] r/w chip temperature detection threshold as below 01 3-1 rpc [2:0] r/w rapid charge current select bits as below 000 0 chgonb r/w charger on/off control bit off on 0 tp [1:0] chip temperature detection threshold 11 135 10 115 01 105 00 95 rpc [2:0] rapid charge current 111 850 ma 110 800 ma 101 750 ma 100 700 ma 011 650 ma 010 600 ma 001 550 ma 000 500 ma bit name r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3 adpbiren r/w over voltage adaptor disconnection interrupt enable enable disable 0 2 adpiren r/w over voltage adaptor connection interrupt enable enable disable 0 1 adpbir r over voltage adaptor disconnection interrupt flag generated none --- 0 adpir r over voltage adaptor connection interrupt flag generated none --- 77 6329a?pmaac?12-aug-07 AT73C206 6.4 a/d converter registers 6.4.1 adccnt: a/d converter control register (address 09h) note: 1. this bit can be cleared by writing ?0? but can not set flag by writing ?1?. 6.4.2 adstart: a/d converter conversion start register (address 0ah) adend: end of the ad conversion bit 1: ad conversion is completed. this bit is cleared by reading the converted data. adstart: start of the ad conversion command 1: start ad conversion this bit is automatically cleared after conversion starts. bit symbol r/w function 1 0 initial value 7-6 ----- ----- reserved ----- ----- ----- 5 bufen r/w buffer enable bit enable disable 0 4 btmen r/w battery monitor enable bit enable disable 0 3 adcecir r/w adc ?end of conversion? interrupt request bit (1) generated none 0 2 adciren r/w adc interrupt enable bit enable disable 0 1-0 adsel [1:0] r/w adc input select as below as below 00 adsel: selecting adc input 11 p1/an1 10 p0/an0 01 imoni 00 batmoni bit symbol r/w function 1 0 initial value 7-2 ----- ----- reserved ----- ----- ----- 1 adend r end of the ad conversion bit as below 0 0 adstart w start of the ad conversion command as below 0 78 6329a?pmaac?12-aug-07 AT73C206 6.4.3 adcdata: conversion data register (address 0bh) bit symbol r/w function 1 0 initial value 7-0 addata [7:0] r conversion data conversion data 0 result adc an0 an1 imoni(v) batmoni(v) 255 vddio vddio vddio vddio x 2 0 0.000 0.000 0.000 0.000 79 6329a?pmaac?12-aug-07 AT73C206 6.5 keypad led registers 6.5.1 kled: keypad led control register (address 0ch) bit symbol r/w function 1 0 initial value gsp=l gsp=h 7-1 ----- ----- reserved ----- ----- ----- ----- 0 kleden r/w enable keyled driver on off 0 0 80 6329a?pmaac?12-aug-07 AT73C206 6.6 clock control register 6.6.1 clkcnt: clock control register (address 0dh) note: this bit can be cleared by writing ?0? but can not set flag by writing ?1?. bit symbol r/w function 1 0 initial value gsp=l gsp=h -3 ----- ----- reserved ----- ----- ----- ----- 2 stpiren r/w clock stop interrupt enable enable disable 0 0 1 stpir r/w clock stop interrupt request flag (note) generated none 0 0 0 ck32en r/w out32k output enable enable disable 1 0 81 6329a?pmaac?12-aug-07 AT73C206 6.7 interrupt request fl ag monitor registers 6.7.1 irqmon1: interrupt request flag monitor 1 register (address 0eh) note: the bit, whose interrupt is prohibited from genera ting by each interrupt enable/disable register bit, has ?0?. 6.7.2 irqmon2: interrupt request flag monitor 2 register (address 0fh) note: the bit, whose interrupt is prohibited from generat ing by each interrupt enable/disable register bit, has ?0?. bit symbol r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3 jackbirm r jack disconnection interrupt flag monitor requested none 0 2 jackirm r jack connection interrupt flag monitor requested none 0 1 adpbirm r over voltage adaptor disconnection interrupt flag monitor requested none 0 0 adpirm r over voltage adaptor connection interrupt flag monitor requested none 0 bit symbol r/w function 1 0 initial value 7-5 ----- --- reserved ----- ----- ----- 4 stpirm r clock stop detection interrupt flag monitor requested none 0 3 adcecirm r adc ?end of conversion? interrupt flag monitor requested none 0 2 ctfgm r rtc ctfg flag monitor requested none 0 1 wafgm r rtc wafg flag monitor requested none 0 0 dafgm r rtc dafg flag monitor requested none 0 82 6329a?pmaac?12-aug-07 AT73C206 6.8 rtc registers 6.8.1 rtc counter registers 6.8.1.1 sec: second counter register (address 10h) 6.8.1.2 min: minute counter register (address 11h) 6.8.1.3 hour: hour counter register (address 12h) digit display(bcd code) second: range is 00 to 59. the second digit is rounded up to the minute digit when the count changes from 59 to 00. minute: range is 00 to 59. the minute digit is rounded up to the hour digit when the count changes from 59 to 00. hour: the hour digit is rounded up to the day or day of the week when the count changes from pm11 to pm12 or from 23 to 00. the lower-order counter than one second counter is reset when the writing second counter is conducted. rounding up from any incorrect and invalid data in the counter register results in unpredictable behavior. only valid and correct data must be written to the counter register. bit7 6543210 symbol reserved s40 s20 s10 s8 s4 s2 s1 r/w --- r/w r/w r/w r/w r/w r/w r/w default --- --- --- --- --- --- --- --- bit7 6543210 symbol reserved m40 m20 m10 m8 m4 m2 m1 r/w --- r/w r/w r/w r/w r/w r/w r/w default --- --- --- --- --- --- --- --- bit7 6 543210 symbol reserved reserved h20pa h10 h8 h4 h2 h1 r/w --- --- r/w r/w r/w r/w r/w r/w default --- --- --- --- --- --- --- --- 83 6329a?pmaac?12-aug-07 AT73C206 6.8.1.4 week: a day of a week counter register (address 13h) when the day digit is rounded up, the digit is incremented by 1. day of week display (septet incremental count): (w4w2w1)=(000) -> (001) -> ...(110) -> (000) correspondence between day of the week and count value are user programmable. (e.g. sunday=000) writing (w4w2w1)=(111) is prohibited except when day of the week is unused. 6.8.1.5 day: day counter register (address 14h) 6.8.1.6 month: month counter and 100year bit register (address 15h) 6.8.1.7 year: year counter register (address 16h) digit display (bcd code) is as follows ac cording to the auto calendar function. day digit: 1 to 31 (january, march, may, july, august, october, and december) 1 to 30 (april, june, september, and november) 1 to 29 (february in a leap year) 1 to 28 (february in regular year) bit76543210 symbol reserved reserved reserved reserved reserved w4 w2 w1 r/w --- --- --- --- --- r/w r/w r/w default --- --- --- --- --- --- --- --- bit7 6 543210 symbol reserved reserved d20 d10 d8 d4 d2 d1 r/w --- --- r/w r/w r/w r/w r/w r/w default --- --- --- --- --- --- --- --- bit7 6 5 43210 symbol reserved reserved reserved mo10 mo8 mo4 mo2 mo1 r/w --- --- --- r/w r/w r/w r/w r/w default --- --- --- --- --- --- --- --- bit76543210 symbol y80 y40 y20 y10 y8 y4 y2 y1 r/w r/wr/wr/wr/wr/wr/wr/wr/w default --- --- --- --- --- --- --- --- 84 6329a?pmaac?12-aug-07 AT73C206 (the day digit is rounded up to the month digit when the count value returns to 1.) month digit: range is 1 to 12. the month digit is rounded up to the year digit when the count value returns to 1. year digit: range is 00 to 99. years 00, 04, 08, ?, 92, 96 are leap years (corresponding to the year 2000 to 2099). rounding up from any incorrect and invalid data in the counter register results in unpredictable behavior of the chip. only valid and correct data must be written to the counter register. 6.8.1.8 rtcadj: rtc adjustment register (address 17h) f6 ~ f0 the count value of one second is changed by the value of this register. normally, the second count is incremented by 32768 clock pulses generat ed by the oscillator. the clock error offset circuit functions by writi ng data to this register. register value f6=?0?: the count value is incremented by ((f5,f4,f3,f2,f1,f0)-1) x 2. register value f6=?1?: the count value is decremented by((/f5,/f4,/f3,/f2,/f1,/f0)+1) x 2. when f6,f5,f4,f3,f2,f1,f0= (*,0,0,0,0,0,*), there is no change in the count value. /f5, /f4, /f3, /f2, /f1, /f0 indicate reversed f5, f4, f3, f2, f1, f0. example when (f6,f5,f4,f3,f2,f1,f0)=(0,0,0,0,1,1,1) and second digit is 00, 20 or 40, the count value becomes 32768+(7-1)t2=32780.it puts clock back. when (f6,f5,f4,f3,f2,f1,f0)=(0,0,0,0,0,0,1) and second digit is 00, 20 or 40, count value is hold at 32768 without making any change. when 2 pulses are added to clock every 20sec, the count value becomes 2/(32768 x 20)=3.051 ppm and the clock will be put ba ck around 3ppm. likewise, when 2 pulses are reduced, 3ppm will be put forward. the clock error c an be regulated in maximum 1.5ppm. but the clock error offset corr ects only clock not oscillator fr equency. (32k clock output not guaranteed.) bit7 6543210 symbol reserved f6 f5 f4 f3 f2 f1 f0 r/w --- r/w r/w r/w r/w r/w r/w r/w default --- --- --- --- --- --- --- --- 85 6329a?pmaac?12-aug-07 AT73C206 6.8.2 rtc alarm_w registers 6.8.2.1 wal_min: alarm_w minute register (address 18h) 6.8.2.2 wal_hour: alarm_w hour register (address 19h) 6.8.2.3 wal_week: alarm_w a day of a week register (address 1ah) alarm_w hour register: register d5 indicates am/pm on 12-hour format (am:0, pm: 1) and 20 wh20pa on 24-hour format. set the alarm register only to correct time for proper alarm operation since incorrect data to the alarm register results in no match between the counter and alarm register. hour digit on 12-hour format: am 0 o?clock -> 12, pm 0 o?clock -> 32 ww0 ~ ww6 correspond to day of the week counter (w4,w2,w1) = (0,0,0) ~ (1,1,0) when ww0 ~ ww6 are all ?0?, alarm_w will not be output. bit7 6543210 symbol reserved wm40 wm20 wm10 wm8 wm4 wm2 wm1 r/w --- r/wr/wr/wr/wr/wr/wr/w default --- --- --- --- --- --- --- --- bit76543210 symbol reserved reserved wh20pa wh10 wh8 wh4 wh2 wh1 r/w --- --- r/w r/w r/w r/w r/w r/w default --- --- --- --- --- --- --- --- bit7 6543210 symbol reserved ww6 ww5 ww4 ww3 ww2 ww1 ww0 r/w --- r/w r/w r/w r/w r/w r/w r/w default --- --- --- --- --- --- --- --- 86 6329a?pmaac?12-aug-07 AT73C206 6.8.3 rtc alarm_d registers 6.8.3.1 dal_min : alarm_d minute register (address 1bh) 6.8.3.2 dal_hour : alarm_d hour register (address 1ch) alarm_d hour register: d5 indicates am/pm on 12-hour format(am:0, pm:1) and dh20pa on 24-hour format. set the alarm register only to correct time for proper alarm operation since incorrect data to the alarm register results in no match occurring between the counter and alarm register. hour digit on 12-hour format: am 0 o?clock -> 12, pm 0 o?clock -> 32 bit7 6543210 symbol reserved dm40 dm20 dm10 dm8 dm4 dm2 dm1 r/w --- r/w r/w r/w r/w r/w r/w r/w default --- --- --- --- --- --- --- --- bit7 6 543210 symbol reserved reserved dh20pa dh10 dh8 dh4 dh2 dh1 r/w --- --- r/w r/w r/w r/w r/w r/w default --- --- --- --- --- --- --- --- 87 6329a?pmaac?12-aug-07 AT73C206 6.8.4 rtccnt1 : rtc control register 1 (address 1eh) z1224 (bit5) [r/w] : 12-hour/24-hour format select bit setting 12-hour /24-hour must be preceded writing of time data. time-digit display table is shown below. scra (bit4) [r/w] the written value in scra (scratch bit) has no effect on rtc operation. and, it is not initialized even at power-off and hold by vsb power. test (bit3) [w] bit name r/w function 1 0 initial value 7 wale r/w alarm_w enable bit enable disable 0 6 dale r/w alarm_d enable bit enable disable 0 5 z1224 r/w selecting 12-hour/24-hour format as below 0 4 scra r/w scratch bit (for user) 1 0 0 3 test w test control bit as below 0 2-0 ct [2:0] r/w constant cycle inte rrupt select bit as below 000 z1224 selecting 12-hour/24-hour format 1 24-hour format 0 am/pm display 12hour format 24-hour format 12-hour format 24-hour format 12-hour format 00 12 (am12) 12 32 (pm12) 01 01 (am 1) 13 21 (pm 1) 02 02 (am 2) 14 22 (pm 2) 03 03 (am 3) 15 23 (pm 3) 04 04 (am 4) 16 24 (pm 4) 05 05 (am 5) 17 25 (pm 5) 06 06 (am 6) 18 26 (pm 6) 07 07 (am 7) 19 27 (pm 7) 08 08 (am 8) 20 28 (pm 8) 09 09 (am 9) 21 29 (pm 9) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11) 88 6329a?pmaac?12-aug-07 AT73C206 it is prohibited to wr ite ?1? to the test bit. ct [2:0] (bit 2,1,0): constant cycle interrupt select bit 1. pulse mode 2 hz, 1 hz for clock is provided. see diagram below for second count-up. figure 6-1. pulse mode diagram there is a delay from falling edge of output in second count-up. and about 1 sec delayed time than rtc will be readable right a fter the falling edge of output. even though second counter is re-written, ir qb goes ?l? once since lower-order counter than one second sec is reset. 2. level mode interrupt cycle is selectable from 1 second, 1 minute, 1 hour or 1 month. second count-up is synchronous with falling of interrupt output. see the timing chart wit h interrupt cycle set at 1 sec- ond below. test test bit 1 test mode (note) read data is fixed ?0?. 0 normal mode ct [2:0] description waveform mode cycle and falling timing 111 level mode *2) 1 time/1 month (every month 1day am 00 o?clock 00 minute 00 second) 110 level mode *2) 1 time/1 hour (every hour, 00 minute 00 second) 101 level mode *2) 1 time/1 min. (every minute, 00 second) 100 level mode *2) 1 time/ 1sec. (simultaneous with second count-up) 011 pulse mode *1) 1hz (duty50%) 010 pulse mode *1) 2hz (duty50%) 001 - ?l? fixed 000 - off(h) ctfg bit irqb pin second count-up rewrite of second count-up 89 6329a?pmaac?12-aug-07 AT73C206 figure 6-2. level mode diagram the interrupt cycle varies 1 time/20 sec or 1 time/1 min when use clock error offset circuit pulse mode: the period of ?l? output pulse fluctuates in maximum 3.784 ms. for example, duty is 500.3784% at 1hz. level mode: the cycle/1 sec fluctuates in maximum 3.784 ms. ctfg bit irqb pin second count-up writing "0" to ctfg second count-up writing "0" to ctfg second count-up 90 6329a?pmaac?12-aug-07 AT73C206 6.8.5 rtccnt2 : rtc control register 2 (address 1fh) xstz (bit5) [r/w]: oscillator stop detection monitor bit when AT73C206 detects oscillator stop at xstz=?1?, it clears ?1? to ?0? . by reading this bit, host judges whether oscillator has stopped. pon (bit4) [r/w]: power-on reset bit once power-supply becomes 0v, pon becomes ?1? and it is kept at ?1? even though power-sup- ply voltage returns to normal operation voltage. the validity of clock and calendar data can be judged by xstz. when pon = ?1?, clock error offset register, control register1 and control register2 (except pon and xstz) become ?0? so that irqb and out32k pins stop outputting. ?0? is only valid value in pon. writing ?1? makes no change. when pon = ?1?, writing to control register 1,2, second counter register and clock error offset register is not possible. (but, pon can be cleared.) scrb (bit3) [r/w] the written value in the scrb (scratch bit) has no effect on rtc operatio n. it will not be initial- ized even at power-off and hold by vsb power. bit name r/w function 1 0 initial value 7-6 ----- ----- reserved ----- ----- ----- 5 xstz r/w oscillator stop detect ion monitor bit as below ----- 4 pon r/w power-on reset bit as below 1 3 scrb r/w scratch bit (for user) 1 0 0 2 ctfg r/w constant cycle in terrupt flag bit as below 0 1 wafg r/w alarm_w flag bit as below 0 0 dafg r/w alarm_d flag bit as below 0 xstz oscillator stop de tection monitor bit 1 normal operation of oscillator 0 oscillator stop detected pon power-on reset bit 1 power-on reset detected 0 normal operation 91 6329a?pmaac?12-aug-07 AT73C206 ctfg (bit2) [r/w]: constant cycle interrupt flag bit ctfg becomes ?1? when constant clock cycle interrupt outputs (irqb pin). ?0? is only valid data in ctfg when constant cycle interrupt is on level mode. wr iting ?0? disables irqb pin ("h"). in next cycle, it will become ?l? again. ?0? is only valid data in ctfg. writing ?1? makes no change. wafg, dafg (bit1, 0): alarm_w flag bit, alarm_d flag bit wafg and dafg are valid only when both wale and dale bits are ?1? . it becomes ?1? and keeps it for about 61us when each alarm set time and present time coincide.only writing ?0? to these bits is valid. by writing ?0? , irqb becomes ?h?(off) and returns ?l? at next alarm set time. writing ?1? makes no change. when both wale and dale bits are ?0? , alarm function is disabled and the reading values of wafg and dafg bits are ?0? . see the below diagram for relation of wafg/ dafg and irqb output. ctfg constant cycle interrupt flag bit 1 constant cycle interr upt output on (l) 0 constant cycle interr upt output off (h) wafg alarm_w flag bit dafg alarm_d flag bit 1 alarm set time detected 1 alarm set time detected 0 alarm set time not detected 0 alarm set time detected wafg(dafg) bit irqb bit 61 us approx 61 us approx write "0" to wafg(dafg) write "0" to wafg(dafg) (alarm set time detect) (alarm set time detect) (alarm set time detect) 92 6329a?pmaac?12-aug-07 AT73C206 6.9 audio registers 6.9.1 pwrcnt: power control register (address 20h) 6.9.2 vmode: voice mode setting register (address 21h) ifen: interface enable bit 1: enable interface 0: disable interface note: lrckio and bckio are ?l? fixed. (but, only when master mode) vfs: setting sample rate of voice codec vformat : setting voice interface format bit symbol r/w function 1 0 initial value 7-6 ----- ----- reserved ----- ----- ----- 5 smicpon r/w smicbias power-on on off 0 4 micpon r/w micbias power- on on off 0 3-2 ----- ----- reserved ----- ----- ----- 1 dauon r/w audio digital block enable bit on off 0 0 dvoon r/w voice digital block enable bit on off 0 bit symbol r/w function 1 0 initial value 7 vasel r/w voice/audio mode select of audio serial interface voice audio 0 6 mssel r/w setting slave/master mode of audio interface slave master 1 5 ifen r/w interface enable bit as below 0 4 vfs r/w setting sampling rate of voice codec as below 0 3-1 ----- ----- reserved ----- ----- ----- 0 vformat r/w setting voice in terface format as below 0 0 vfs sampling rate 1 16khz 08khz vformat format 1 left justify 0 iis 93 6329a?pmaac?12-aug-07 AT73C206 6.9.3 amode: audio mode setting register (address 22h) afs [2:0]: setting sample rate of audio dac aformat [1:0]: setting audio interface format bit symbol r/w function 1 0 initial value 7 ----- ----- reserved ----- ----- ----- 6-4 afs [2:0] r/w setting sampling rate of audio dac as below 000 3-2 ----- ----- reserved ----- ----- 1-0 aformat [1:0] r/w setting audio interface format as below 00 afs [2:0] sampling rate afs [2:0] sampling rate 111 8khz 011 24khz 110 11.025khz 010 32khz 101 16khz 001 44.1khz 100 22.05khz 000 48khz aformat [1:0] format aformat [1:0] format 11 don?t use 01 left justify 10 right justify 00 iis 94 6329a?pmaac?12-aug-07 AT73C206 6.9.4 omode: codec output mode control register (address 23h) modeco [3:0]: controlling codec output mode bit symbol r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3-0 modeco [3:0] r/w controlling codec output mode as below 0000 modeco[3:0] driver amplifier function receiver speaker headphone receiver speaker 1111 to 1001 - - - reserved reserved 1000 off off on audio mono 0111 off off on audio stereo 0110 off on off audio mono 0101 on off off audio mono 0100 off off on voice - 0011 off on off voice - 0010 on off off voice - 0001 off off off standby mode 0000 off off off power down mode 95 6329a?pmaac?12-aug-07 AT73C206 6.9.5 mute: mute setting register (address 24h) note: when set mute(only for muteda and muteside), the gain changes to mute(gain=0) with 1db decrement per fs. when cancel mute, the gain returns back to former gain value with 1db incre- ment per fs as the former gain value is maintained during mute mode. bit symbol r/w function 1 0 initial value 7-6 ----- ----- reserved ----- ----- ----- 5 muteda r/w audio dac mute on off 1 4 muteside r/w sidetone mute on off 1 3 ----- ----- reserved ----- ----- ----- 2 mutedrv r/w driver amp mute on off 1 1 mutesmic r/w smic mute on off 1 0 mutemic r/w mic mute on off 1 96 6329a?pmaac?12-aug-07 AT73C206 6.9.6 drvag: analog driver gain setting register (address 25h) bit symbol r/w function 1 0 initial value 7-5 ----- ----- reserved ----- ----- ----- 4-0 drvag [4:0] r/w analog driver gain as below 0000 drvag [4:0] gain (db) drvag [4:0] gain (db) 11111 6 01111 -18 11110 4.5 01110 -19.5 11101 3 01101 -21 11100 1.5 01100 -22.5 11011 0 01011 -24 11010 -1.5 01010 -25.5 11001 -3 01001 -27 11000 -4.5 01000 -28.5 10111 -6 00111 -30 10110 -7.5 00110 -31.5 10101 -9 00101 -33 10100 -10.5 00100 -34.5 10011 -12 00011 -36 10010 -13.5 00010 -37.5 10001 -15 00001 -39 10000 -16.5 00000 -40.5 97 6329a?pmaac?12-aug-07 AT73C206 6.9.7 micag: analog mic gain setting register (address 26h) bit symbol r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3-0 micag [3:0] r/w analog mic gain as below 0000 micag [3:0] gain (db) micag [3:0] gain (db) 1111 30 0111 14 1110 28 0110 12 1101 26 0101 10 1100 24 0100 8 1011 22 0011 6 1010 20 0010 4 1001 18 0001 2 1000 16 0000 0 98 6329a?pmaac?12-aug-07 AT73C206 6.9.8 micdg: voice codec tx-data1(mic path) digital gain setting register (address 27h) note: gain changes to the current set value by smoothing gain control at 1db/fs. bit symbol r/w function 1 0 initial value 7-5 ----- ----- reserved ----- ----- ----- 4-0 micdg [4:0] r/w voice codec tx-data1 digital gain as below 00000 micdg [4:0] gain (db) 11111 20 11110 19 11101 18 11100 17 -- (-1db step) -- 00011 -8 00010 -9 00001 -10 00000 mute 99 6329a?pmaac?12-aug-07 AT73C206 6.9.9 sidedg: voice codec sidetone-data digital gain setting register (address 2ah) note: gain changes to the current set value by smoothing gain control at 1db/fs. bit symbol r/w function 1 0 initial value 7-6 ----- ----- reserved ----- ----- ----- 5-0 sidedg [5:0] r/w voice codec sidetonedata digital gain as below 111111 sidedg [5:0] gain (db) 111111 mute 111110 -62 111101 -61 111100 -60 -- (-1db step) -- 000011 -3 000010 -2 000001 -1 000000 0 100 6329a?pmaac?12-aug-07 AT73C206 6.9.10 recdg: voice codec rx-data digital gain setting register (address 2bh) note: gain changes to the current set value by smoothing gain control at 1db/fs. bit symbol r/w function 1 0 initial value 7-5 ----- ----- reserved ----- ----- ----- 4-0 recdg [4:0] r/w voice codec rx-data digital gain as below 00000 recdg [4:0] gain (db) 11111 0 11110 -1 11101 -2 11100 -3 -- (-1db step) -- 00011 -28 00010 -29 00001 -30 00000 mute 101 6329a?pmaac?12-aug-07 AT73C206 6.9.11 dattl: audio dac l-channel digita l gain setting register (address 2ch) 6.9.12 dattr: audio dac r-channel digita l gain setting register (address 2dh) gain changes to the current set value by smoothing gain control at 1db/fs. bit symbol r/w function 1 0 initial value 7-6 ----- ----- reserved ----- ----- ----- 5-0 dattl [5:0] r/w audio dac l-channel digital gain as below 111111 bit symbol r/w function 1 0 initial value 7-6 ----- ----- reserved ----- ----- ----- 5-0 dattr [5:0] r/w audio dac r-channel digital gain as below 111111 dattl [5:0] dattr [5:0] gain (db) 111111 mute 111110 -62 111101 -61 111100 -60 -- (-1db step) -- 000011 -3 000010 -2 000001 -1 000000 0 102 6329a?pmaac?12-aug-07 AT73C206 6.9.13 tncnt: tone control register (address 2fh) note: setting tncon bit lets the tone generator gener ate tone for the time se t by tntime bits. after timer overflows, it stops tone and clears tnco n bit automatically. setting tncon is available when voice block and pll block for voice are powered-on. bit symbol r/w function 1 0 initial value 7 tncon r/w controlling tone generator on off 0 6 vrtnsw r/w mixing rx voice data and tone data mix not mix 0 5 vttnsw r/w mixing tx voice data and tone data mix not mix 0 4 ----- ----- reserved ----- ----- ----- 3-0 tntime [3:0] r/w setting time of hardware tone timer as below 0010 tntime [3:0] time (ms) tntime [3:0] time (ms) 1111 continuous output 0111 150 1110 don?t use (100) 0110 140 1101 don?t use (100) 0101 130 1100 200 0100 120 1011 190 0011 110 1010 180 0010 100 1001 170 0001 90 1000 160 0000 80 103 6329a?pmaac?12-aug-07 AT73C206 6.9.14 tnset: type of generated tone& tone gain setting register (address 30h) tng3: setting tone3 gain freqsel: setting type of generated tone bit symbol r/w function 1 0 initial value 7-5 tng3 [2:0] r/w setting tone3 gain as below 111 4-0 freqsel [4:0] r/w setting type of generated tone as below 00000 tng3 [2:0] gain (db) tng3 [2:0] gain (db) 111 -42 011 -18 110 -36 010 -12 101 -30 001 -6 100 -24 000 0 freqsel [4:0] dtmf tone1 frequency tone2 frequency 0 0000 dtmf ?1? 1209 hz 697 hz 0 0001 dtmf?2? 1336 hz 0 0010 dtmf?3? 1477 hz 0 0011 dtmf?a? 1633 hz 0 0100 dtmf?4? 1209 hz 770 hz 0 0101 dtmf?5? 1336 hz 0 0110 dtmf?6? 1477 hz 0 0111 dtmf?b? 1633 hz 0 1000 dtmf?7? 1209 hz 852 hz 0 1001 dtmf?8? 1336 hz 0 1010 dtmf?9? 1477 hz 0 1011 dtmf?c? 1633 hz 0 1100 dtmf?*? 1209 hz 941 hz 0 1101 dtmf?0? 1336 hz 0 1110 dtmf?#? 1477 hz 0 1111 dtmf?d? 1633 hz 1 xxxx - programmable tone1 programmable tone2 104 6329a?pmaac?12-aug-07 AT73C206 6.9.15 tngain: tone gain setting register (address 31h) bit symbol r/w function 1 0 initial value 7-4 tng2 [3:0] r/w setting tone2 gain as below 1111 3-0 tng1 [3:0] r/w setting tone1 gain as below 1111 tng1, 2 [3:0] gain (db) tng1, 2 [3:0] gain (db) 1111 -15 0111 -7 1110 -14 0110 -6 1101 -13 0101 -5 1100 -12 0100 -4 1011 -11 0011 -3 1010 -10 0010 -2 1001 -9 0001 -1 1000 -8 0000 0 105 6329a?pmaac?12-aug-07 AT73C206 6.9.16 ptn1setl: programmable tone 1 frequency setting register l (address 32h) 6.9.17 ptn1seth: programmable tone 1 frequency setting register h (address 33h) 6.9.18 ptn2setl: programmable tone 2 frequency setting register l (address 34h) 6.9.19 ptn2seth: programmable tone 2 frequency setting register h (address 35fh) frequency of programmable tone1 = 7.8125hz x ptone1 from 0hz to 3992.1875hz frequency of programmable tone2 = 7.8125hz x ptone2 from 0hz to 3992.1875hz bit symbol r/w function 1 0 initial value 7-0 ptn1 [7:0] r/w setting frequency of programmable tone1 as below 00000000 bit symbol r/w function 1 0 initial value 7-1 ----- ----- reserved ----- ----- 0 ptn1 [8] r/w setting frequency of programmable tone1 as below 0 bit symbol r/w function 1 0 initial value 7-0 ptn2 [7:0] r/w setting frequency of programmable tone2 as below 00000000 bit symbol r/w function 1 0 initial value 7-1 ----- ----- reserved ----- ----- 0 ptn2 [8] r/w setting frequency of programmable tone2 as below 0 106 6329a?pmaac?12-aug-07 AT73C206 6.9.20 apllcnt: audio pll contro l register (address 36h) ckosel: output clock select apllsrc: setting input clock to pll for audio note: use this mode with setting adivn and adivm. bit symbol r/w function 1 0 initial value 7 apllpon r/w audio pll power-on on off 0 6-4 ckosel [2:0] r/w output clock select as below 000 3-1 ----- ----- reserved ----- ----- ----- 0 apllsrc r/w setting input clock to pll for audio as below 0 ckosel [2:0 ckout pin output clock 000 ?l? fixed. 001 32.768khz 010 f a 011 f a / 2 100 f a / 4 101 f a / 8 110 - 111 - apllsrc mode 1 external clock input and programmable mode (note) 0 internal x?tal (32.768khz) mode 107 6329a?pmaac?12-aug-07 AT73C206 6.9.21 vpllcnt: voice vpll control register (address 37h) note: use this mode with setting vdivn and vdivm. bit symbol r/w function 1 0 initial value 7 vpllpon r/w voice pll power-on on off 0 6-1 ----- ----- reserved ----- ----- ----- 0 vpllsrc r/w setting input clock to pll for voice as below 0 vpllsrc mode 1 external clock input and programmable mode (note) 0 internal x?tal (32.768khz) mode 108 6329a?pmaac?12-aug-07 AT73C206 6.9.22 adivnl: divide factor-n for audio setting register l (address 38h) 6.9.23 adivnh: divide factor-n for audio setting register h (address 39h) na= adivn + 1 6.9.24 adivml: divide factor-m for audio setting register l (address 3ah) 6.9.25 adivmh: divide factor-m for audio setting register h (address 3bh) ma= adivm + 1 bit symbol r/w function 1 0 initial value 7-0 adivn[7:0] r/w setting divide factor-n for audio as below 00000000 bit symbol r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3-0 adivn[11:8] r/w setting divide factor-n for audio as below 0000 bit symbol r/w function 1 0 initial value 7-0 adivm[7:0] r/w setting divide factor-m for audio as below 00000000 bit symbol r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3-0 adivm[11:8] r/w setting divide factor-m for audio as below 0000 109 6329a?pmaac?12-aug-07 AT73C206 6.9.26 vdivnl: divide factor-n for voice setting register l (address 3ch) 6.9.27 vdivnh: divide factor-n for voice setting register h (address 3dh) nv= vdivn + 1 6.9.28 vdivml: divide factor-m for voice setting register l (address 3eh) 6.9.29 vdivmh : divide factor-m for voice setting register h (address 3fh) mv= vdivm + 1 bit symbol r/w function 1 0 initial value 7-0 vdivn[7:0] r/w setting divide factor-n for voice as below 00000000 bit symbol r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3-0 vdivn[11:8] r/w setting divide factor-n for voice as below 0000 bit symbol r/w function 1 0 initial value 7-0 vdivm[7:0] r/w setting divide factor-m for voice as below 00000000 bit symbol r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3-0 vdivm[11:8] r/w setti ng divide factor-m for voice as below 0000 110 6329a?pmaac?12-aug-07 AT73C206 6.10 status monitor register 6.10.1 stmon: status monitor register (address 40h) bit symbol r/w function 1 0 initial value 7-3 ----- ----- reserved ----- ----- ----- 2 jackmon r jack detector monitor bit inserted removed ----- 1 clkstpmon r 32khz osc stop detect ion monitor bit stop oscillate ----- 0 onswmon r onsw pin input monitor bit h l ----- 111 6329a?pmaac?12-aug-07 AT73C206 6.11 general purpose i/o registers 6.11.1 gpiodir: gpio direction control register (address 41h) note: gpiodir becomes invalid by selecting analog input mode. 6.11.2 gposet: gpio output setting register (address 42h) 6.11.3 gpimon: gpio input status register (address 43h) note: when analog input mode is selected, this register will be set to ?0?. bit symbol r/w function 1 0 initial value 7-6 ----- ----- reserved ----- ----- ----- 5 gpain1 r/w input signal mode digital analog 0 4 gpain0 r/w input signal mode digital analog 0 3 gpiodir3 r/w gpio3 direction control bit out in 0 2 gpiodir2 r/w gpio2 direction control bit out in 0 1 gpiodir1 r/w gpio1 direction control bit out in 0 0 gpiodir0 r/w gpio0 direction control bit out in 0 bit symbol r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3 gposet3 r/w gpio3output logic setting bit h l 0 2 gposet2 r/w gpio2 output logic setting bit h l 0 1 gposet1 r/w gpio1 output logic setting bit h l 0 0 gposet0 r/w gpio0 output logic setting bit h l 0 bit symbol r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3 gpimon3 r gpio3 input status bit h l - 2 gpimon2 r gpio2 input status bit h l - 1 gpimon1 r gpio1 input status bit h l - 0 gpimon0 r gpio0 input status bit h l - 112 6329a?pmaac?12-aug-07 AT73C206 6.12 jackdet control register 6.12.1 jackcnt : jackdet control register (address 44h) bit symbol r/w function 1 0 initial value 7-4 ----- ----- reserved ----- ----- ----- 3 jkbiren r/w jack disconnection interrupt enable enable disable 0 2 jkiren r/w jack connection interrupt enable enable disable 0 1 jackbir r jack disconnection interrupt flag generate d none ----- 0 jackir r jack connection interrupt flag generate d none ----- 113 6329a?pmaac?12-aug-07 AT73C206 7. dc electrical characteristics 7.1 absolute maximum ratings the operation exceeding the below ?absolute maximum ratings? may cause permanent damage to the device. the operation of the device within the below stated ratings is not guaranteed. vcc = v bat ,v dd note: 1. derating 36[mw/ c] above +70 c. 7.2 recommendation operating conditions table 7-1. absolute maximum ratings symbol parameter condition rated value units v bat vbat power pin voltage vin1 to 6, vbsp -0.3 to 6.0 v v chg ac-adaptor voltage input pins vchgadp -0.3 to 7.0 v v dd vdd power pin voltage vddpll, vdd, vddhp, vddana, vddio -0.3 to 4.5 v v sb backup part (rtc) vsb -0.3 to 4.5 v v dc ldo1 power pin voltage vdc1 -0.3 to 3.6 v v din din pin input voltage din1 to 4 -0.3 to 7.0 v v pin input voltage range all inpu t pins -0.3 to vcc + 0.3 v pd package allowable dissipation (1) mounted on board, t a = 70 c 1500 mw t stg storage temperature ----- -55 to +125 c table 7-2. recommended operating conditions symbol parameter condition min typ max units v bat vbat power pin voltag e vin16, vbsp 3.1 3.6 4.2 v v chg ac-adaptor voltage inpu t pins vchgadp 4.5 5.0 5.5 v v dd vdd power pin voltage vddpll, vdd, vddhp, vddana -3% 2.8 +3% v v dd2 vdd power pin voltage vddio -3% 2.5 +3% v v sb backup part (rtc) vsb 1.6 3.0 v v dc ldo1 power pin voltage vdc1 -3% 1.8 +3% v t a temperature of operation -30 +85 114 6329a?pmaac?12-aug-07 AT73C206 7.3 vbat cmos input pin application: ldo1sel, gsp 7.4 vbat cmos schmitt i nput pin with pull-down application: onsw 7.5 vbat cmos schmitt i nput pin with pull-down application: smpl table 7-3. electrical characteristics symbol parameter condition min typ max unit ili input leakage current vin =0vin -1 1 ua vih input voltage ?h? level vin x 0.7 v vil input voltage ?l? level vin x 0.3 v table 7-4. electrical characteristics symbol parameter condition min typ max unit iil ?l? input leakage current vin =0 -1 1 ua rpd pull-down resistance 1 m ? vt+ input rise threshold voltage vin x 0.5 vin x 0.8 v vt- input fall threshold voltage vin x 0.2 vin x 0.5 v vt hysteresis vin x 0.15 v table 7-5. electrical characteristics symbol parameter condition min typ max unit iil ?l? input leakage current vin =0 -1 1 ua rpd pull-down resistance 1 m ? vt+ input rise threshold voltage 1.4 v vt- input fall threshold voltage 0.6 v vt hysteresis 0.8 v 115 6329a?pmaac?12-aug-07 AT73C206 7.6 vddio cmos input pin application: pshold, sdi, sen, sclk 7.7 vddio cmos output pin application: sdo, adpinb, irqb, out32k, rstb, onob 7.8 vddio cmos i/o pin application: p3, p2, p1/an1, p0/an0 table 7-6. electrical characteristics symbol parameter condition min typ max unit ili input leakage current vin =0vddio -1 1 ua vih input voltage ?h? level vddiot0.7 v vil input voltage ?l? level vddiot0.3 v table 7-7. electrical characteristics symbol parameter condition min typ max unit voh output voltage ?h? level iout=-2ma vddio - 0.4 v vol output voltage ?l? level iout=2ma 0.4 v table 7-8. electrical characteristics symbol parameter condition min typ max unit ili input leakage current vin =0vddio -1 1 ua vih input voltage ?h? level vddio x 0.7 v vil input voltage ?l? level vddio x 0.3 v voh output voltage ?h? level iout=-2ma vddio - 0.4 v vol output voltage ?l? level iout=2ma 0.4 v 116 6329a?pmaac?12-aug-07 AT73C206 7.9 vdd cmos input pin application: din, ckin 7.10 vdd cmos schmitt i nput pin with pull-up application: jkdeti 7.11 vdd cmos output pin application: jkdeto, dout, ckout 7.12 vdd cmos i/o pin application: lrckio, bckio table 7-9. electrical characteristics symbol parameter condition min typ max unit ili input leakage current vin =vdd -1 1 ua vih input voltage ?h? level vdd x 0.7 v vil input voltage ?l? level vdd x 0.3 v table 7-10. electrical characteristic symbol parameter condition min typ max unit iih ?h? input leakage current vin =vdd -1 1 ua rpu pull-up resistance 200 k ? vt+ input rise threshold voltage vdd x 0.5 vdd x 0.8 v vt- input fall threshold voltage vdd x 0.2 vdd x 0.5 v vt hysteresis vdd x 0.1 v table 7-11. electrical characteristics symbol parameter condi tion min typ max unit voh output voltage ?h? level iout=-2ma vdd ? 0.4 v vol output voltage ?l? level iout=2ma 0.4 v table 7-12. electrical characteristics symbol parameter condition min typ max unit ili input leakage current vin =0vdd -1 1 ua vih input voltage ?h? level vdd x 0.7 v vil input voltage ?l? level vdd x 0.3 v voh output voltage ?h? level iout=-2ma vdd ? 0.4 v vol output voltage ?l? level iout=2ma 0.4 v 117 6329a?pmaac?12-aug-07 AT73C206 8. revision history table 8-1. document ref. comments change request ref. 6329a first issue 6329a?pmaac?12-aug-07 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com www.atmel.com/powermgmt technical support pmaac@atmel.com sales contacts www.atmel.com/contacts/ literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, expr ess or implied, by estoppel or otherwise, to any intellectual property right is granted by this document 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